ICS9FG1200D-1 Datasheet, PDF (17/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2

ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
SMBusTable: Reserved Register
Byte 16 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function Type
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1
PWD
0
0
0
0
0
0
0
0
SMBus Table: 1:1 PLL Frequency Control Register
Byte 17 Pin #
Name
Control Function Type
0
1
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
-
1:1 PLL M Div5
RW
Bit 4
-
Bit 3
-
1:1 PLL M Div4
1:1 PLL M Div3
RW
M Divider Programming RW Contact IDT for 9FG1200-
Bit 2
-
1:1 PLL M Div2
bits
RW 1 M/N programming Table
Bit 1
-
1:1 PLL M Div1
RW
Bit 0
-
1:1 PLL M Div0
RW
PWD
0
0
X
X
X
X
X
X
SMBus Table: 1:1 PLL Frequency Control Register
Byte 18 Pin #
Name
Control Function Type
0
1
Bit 7
-
1:1 PLL N Div7
RW
Bit 6
-
1:1 PLL N Div6
RW
Bit 5
-
1:1 PLL N Div5
RW
Bit 4
-
1:1 PLL N Div4 N Divider Programming RW Contact IDT for 9FG1200-
Bit 3
-
1:1 PLL N Div3
bits
RW 1 M/N programming Table
Bit 2
-
1:1 PLL N Div2
RW
Bit 1
-
1:1 PLL N Div1
RW
Bit 0
-
1:1 PLL N Div0
RW
PWD
X
X
X
X
X
X
X
X
SMBusTable: 1:1 PLL Output Divider Register
Byte 19 Pin #
Name
Control Function Type
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
RESERVED
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1outDiv 3
1outDiv 2
1outDiv 1
1outDiv 1
RESERVED
RW
1:1 Output Divider
RW
RW
RW
0
1
Contact IDT for Output
Divider Table
PWD
0
0
0
0
X
X
X
X
IDT^® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
17
1138C 02/08/10