ICS9FG1200D-1 Datasheet, PDF (6/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2

ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
9FG1200-1 1:1 PLL Programming
Byte 8,
Byte 8,
Byte 8,
CLK_IN
1:1 DIF
bit 2
bit 1
bit 0
(CPU FSB) Outputs
FSC
FSB
FS_A_410
MHz
MHz
1
0
1
100.00
100.00
0
0
1
133.33
133.33
0
1
1
166.67
166.67
0
1
0
200.00
200.00
0
0
0
266.67
266.67
1
0
0
333.33
333.33
1
1
0
400.00
400.00
1
1
1
Reserved
Notes
3
3
1
3
3
3
2
Notes:FS_A_410 = 1
1. Powerup Default for FS_A_410 = 1
2. Powerup Default for FS_A_410 = 0
3. Setting the exact FSB frequency after Power up is required for best phase noise performance.
IDT^® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
6
1138C 02/08/10