ICS9FG1200D-1 Datasheet, PDF (3/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2

ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Pin Description
PIN # PIN NAME
1
HIGH_BW#
2
CLK_IN
3
CLK_IN#
4
SMB_A0
5
OE0#
6
DIF_0
7
DIF_0#
8
OE1#
9
DIF_1
10 DIF_1#
11 VDD
12 GND
13 DIF_2
14 DIF_2#
15 OE2#
16 DIF_3
17 DIF_3#
18 OE3#
19 DIF_4
20 DIF_4#
21 OE4#
22 VDD
23 GND
24 DIF_5
25 DIF_5#
26 OE5#
27 SMB_A1
28 SMBDAT
PIN TYPE
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
PWR
PWR
OUT
OUT
IN
IN
I/O
DESCRIPTION
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Input for reference clock.
"Complementary" reference clock input.
SMBus address bit 0 (LSB)
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
SMBus address bit 1
Data pin of SMBUS circuitry, 5V tolerant
IDT^® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
3
1138C 02/08/10