ICS9FG1200D-1 Datasheet, PDF (10/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2

ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Electrical Characteristics - Phase Jitter
PARAMETER SYMBOL
CONDITIONS
MIN TYP. MAX
PCIe Gen 1 REFCLK phase jitter
t_jphPCIe1
(including PLL BW 8 - 16 MHz,
ζ = 0.54,
43/37 86
Td=10 ns, Ftrk=1.5 MHz )
PCIe Gen 2 REFCLK phase jitter
t_jphPCIe2Lo
(including PLL BW 8 - 16 MHz,
ζ = 0.54, Td=12 ns)
Lo-band content
1.2/1.3 3
(10kHz to 1.5MHz)
Jitter, Phase
t_jphPCIe2Hi
PCIe Gen 2 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54, Td=12 ns)
Hi-band content
3.0/2.4 3.1
(1.5MHz to Nyquist)
t_{jphFBD1_3.2G}
FBD REFCLK phase jitter
(including PLL BW 11 - 33 MHz,
ζ = 0.54, Td=12 ns Ftrl=0.2MHz)
2.5/2.1 3
FBD REFCLK phase jitter
t_{jphFBD1_4.8G}
(including PLL BW 11 - 33 MHz,
2.0/1.6 2.5
ζ = 0.54, Td=12 ns Ftrl=0.2MHz)
Notes on Phase Jitter:
1 _{See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production.}
2 _{Device driven by 932S421BGLF or equivalent}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1}-12
4 _{Hi-Bandwidth Number/Low Bandwidth Number with Spread On. Spread Off gives lower numbers.}
UNITS
ps
ps rms
ps rms
ps
(RMS)
ps
(RMS)
NOTES
1,2,3
1,2
1,2
1,2
1,2
IDT^® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
10
1138C 02/08/10