ICS842S104 Datasheet, PDF (8/21 Pages) Integrated Device Technology – Crystal-to-HSTL 100MHz / 200MHz PCI Express™ Clock Synthesizer

ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum
Fundamental
25
50
7
Units
MHz
Ω
pF
AC Electrical Characteristics
Table 6. AC Characteristics, V_DD = 3.3V ± 5%, T_A = 0°C to 70°C
Symbol
Parameter
Test Conditions
f_MAX
Output Frequency
FOUTCTL = 0
FOUTCTL = 1
fref
Reference frequency
t_{REFCLK_HF_RMS} Phase Jitter RMS; NOTE 1, 2
ƒ= 200MHz,
25MHz crystal input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
t_{REFCLK_LF_RMS} Phase Jitter RMS; NOTE 1
ƒ= 200MHz,
25MHz crystal input
Low Band: 10kHz - 1.5MHz
tsk(o)
Output Skew; NOTE 2, 3
tjit(Ø)
Phase Jitter, RMS (Random)
200MHz, Integration Range:
12kHz – 20MHz
tjit(cc)
Cycle-to-Cycle Jitter
PLL Mode
t_L
PLL Lock Time
odc
Output Duty Cycle
Minimum
Typical
100
200
25
Maximum
Units
MHz
MHz
0.95
ps
0.31
ps
50
ps
1.27
ps
25
ps
60
ms
48
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for t_{REFCLK_HF_RMS} (High
Band) and 3.0 ps RMS for t_{REFCLK_LF_RMS} (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also the
PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
ICS842S104CG REVISION A MARCH 17, 2010
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©2010 Integrated Device Technology, Inc.