ICS842S104 Datasheet, PDF (18/21 Pages) Integrated Device Technology – Crystal-to-HSTL 100MHz / 200MHz PCI Express™ Clock Synthesizer

ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the HSTL output pair.
HSTL output driver circuit and termination are shown in Figure 6.
V_DDO
Q1
V_OUT
RL
50Ω
Figure 6. HSTL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V_{OH_MAX} /R_L) * (V_{DD_MAX} - V_{OH_MAX})
Pd_L = (V_{OL_MAX} /R_L) * (V_{DD_MAX} - V_{OL_MAX})
Pd_H = (1.2V/50Ω) * (2.0V - 1.2V) = 19.2mW
Pd_L = (0.4V/50Ω) * (2.0V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
ICS842S104CG REVISION A MARCH 17, 2010
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