ICS842S104 Datasheet, PDF (4/21 Pages) Integrated Device Technology – Crystal-to-HSTL 100MHz / 200MHz PCI Express™ Clock Synthesizer

ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER
Table 3B. Block Read and Block Write Protocol
Bit
Description = Block Write
1
Start
2:8
Slave address - 7 bits
9
Write
10
Acknowledge from slave
11:18
Command Code - 8 bits
19
Acknowledge from slave
20:27
Byte Count - 8 bits
28
Acknowledge from slave
29:36
Data byte 1 - 8 bits
37
Acknowledge from slave
38:45
Data byte 2 - 8 bits
46
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N - 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
Description = Block Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave - 8 bits
Acknowledge
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from Slave/Acknowledge
Data Byte N from slave - 8 bits
Not Acknowledge
Table 3C. Byte Read and Byte Write Protocol
Bit
Description = Byte Write
1
Start
2:8
Slave address - 7 bits
9
Write
10
Acknowledge from slave
11:18
Command Code - 8 bits
19
Acknowledge from slave
20:27
Data Byte - 8 bits
28
Acknowledge from slave
29
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39
Description = Byte Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Data from slave - 8 bits
Not Acknowledge
Stop
ICS842S104CG REVISION A MARCH 17, 2010
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