ICS842S104 Datasheet, PDF (11/21 Pages) Integrated Device Technology – Crystal-to-HSTL 100MHz / 200MHz PCI Express™ Clock Synthesizer

ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS842S104 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. V_DD, V_DDA and V_DDO should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic V_DD pin and also shows that V_DDA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the V_DDA pin.
3.3V
V_CC
.01µF _10Ω
V_CCA
.01µF
10µF
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
HSTL Outputs
All unused HSTL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
ICS842S104CG REVISION A MARCH 17, 2010
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©2010 Integrated Device Technology, Inc.