ICS842S104 Datasheet, PDF (14/21 Pages) Integrated Device Technology – Crystal-to-HSTL 100MHz / 200MHz PCI Express™ Clock Synthesizer

ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER
Schematic Example
Figure 5 shows an example of ICS842S104 application schematic. In
this example, the device is operated at V_DD = 3.3V and V_DDO = 1.8V.
Both input options are shown. The device can either be driven using
a quartz crystal or a 3.3V LVCMOS signal. The C1 and C2 = 18pF
are recommended for frequency accuracy. For different board
layouts, the C1 and C2 may be slightly adjusted for optimizing
fequency accuracy. The LVHSTL output driver termination examples
are shown in this schematic. The decoupling capacitor should be
located as close as possible to the power pin.
Logic Control Input Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VDD
VDDO
SRCT1
Zo = 50 Ohm
SRCC1
+
Zo = 50 Ohm
-
R1
R2
U1
50
50
VDD=3.3V
VDDO=1.8V
VDD
R3
10
VDDA
C3
10uF
VDD
R6 R7
SP SP
C4
0.01u
VDD
25MHz
C2
18pF
X1 _{1 8 p F}
C1
18pF
J1
R8
0
5 SDA
4
3
2
R9
0
1 SCL
SRCT4
Zo = 50 Ohm
SRCC4
+
VDDO
Zo = 50 Ohm
-
R4
R5
50
50
VDD
(U1-10)
(U1-17)
VDD
C5
0.1uF
C6
0.1uF
VDDO
(U1-4)
(U1-22)
VDDO
C7
0.1uF
C8
0.1uF
Figure 5. ICS842S104 Schematic Example
ICS842S104CG REVISION A MARCH 17, 2010
14
©2010 Integrated Device Technology, Inc.