ICS842S104 Datasheet, PDF (1/21 Pages) Integrated Device Technology – Crystal-to-HSTL 100MHz / 200MHz PCI Express™ Clock Synthesizer

Crystal-to-HSTL 100MHz / 200MHz
PCI Express™ Clock Synthesizer
ICS842S104
DATA SHEET
General Description
The ICS842S104 is a PLL-based clock generator specifically
designed for PCI Express™ Clock Generation 2 applications. This
device generates either a 200MHz or 100MHz differential HSTL
clock from an input reference of 25MHz. The input reference may be
derived from an external source or by the addition of a 25MHz
crystal to the on-chip crystal oscillator. An external reference is
applied to the XTAL_IN pin with the XTAL_OUT pin left floating.The
device offers spread spectrum clock output for reduced EMI
applications. An I²C bus interface is used to enable or disable spread
spectrum operation as well as select either a down spread value of
-0.35% or -0.5%.The ICS842S104 is available in a lead-free 24-Lead
package.
Features
• Four differential HSTL output pairs
• Crystal oscillator interface: 25MHz
• Output frequency: 100MHz or 200MHz
• RMS phase jitter @ 200MHz (12kHz – 20MHz): 1.27ps (typical)
• Cycle-to-cycle jitter: 25ps (maximum)
• I²C support with readback capabilities up to 400kHz
• Spread Spectrum for electromagnetic interference (EMI) reduction
• 3.3V core/1.5V to 2.0V output operating supply
• 0°C to 70°C ambient operating temperature
• Available lead-free (RoHS 6) package
• PCI Express Gen2 Jitter Compliant
HiPerClockS™
Block Diagram
25MHz
XTAL_IN
XTAL_OUT
OSC
SDATA ^Pullup
SCLK ^Pullup
PLL
I²C
Logic
Divider
Network
4 _SRCT[1:4]
4 _SRCC[1:4]
Pin Assignment
SRCT3 1
SRCC3 2
V_SS 3
VDDO 4
SRCT2 5
SRCC2 6
SRCT1 7
SRCC1 8
VSS 9
VDD 10
VSS 11
nc 12
24 SRCC4
23 SRCT4
22 VDDO
21 SDATA
20 SCLK
19 XTAL_OUT
18 XTAL_IN
17 VDD
16 VSS
15 nc
14 VDDA
13 VSS
ICS842S104
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
ICS842S104CG REVISION A MARCH 17, 2010
1
©2010 Integrated Device Technology, Inc.