932SQL450 Datasheet, PDF (8/23 Pages) Integrated Device Technology – Integrated 85 ohm differential terminations

932SQL450 DATASHEET
Functionality and CPU SAS Frequency Tables
932SQL450 Functionality
CPU
100
SRC
100
PCI
33.33
REF
14.318
NS_SAS
NS_SRC
100.00
DOT96
96.00
USB
48.00
MHz
Spread Spectrum Control Functionality
SS_Enable CPU, SRC &
(B1b0)
PCI
0
OFF
1
-0.50%
932SQL450 Power Down Functionality
CKPWRGD#/PD
1
Differential
Outputs
Low/Low
Single-
ended
Outputs
Low
Single-
ended
Outputs
w/Latch
Low¹
0
Running
1. Single-ended outputs with a Latch will be Hi-Z until
the first application of CKPWRGD#.
CPU/SRC/PCI Margining Table
Line
Byte6 Byte6 Byte6
Bit2 Bit1 Bit0
FS2 FS1 FS0
CPU
Speed
(MHz)
SRC PCI
(MHz) (MHz)
0
0
0
0
97.00 97.00 32.33
1
0
0
1
98.00 98.00 32.67
2
0
1
0
99.00 99.00 33.00
3
0
1
1
100.00 100.00 33.33 Default for 100MHz
4
1
0
0
101.00 101.00 33.67
5
1
0
1
102.00 102.00 34.00
6
1
1
0
103.00 103.00 34.33
7
1
1
1
104.00 104.00 34.67
Line
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NS_SAS Margining Table
Byte5
Bit3
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Byte5
Bit2
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Byte5 Byte5
Bit1 Bit0
FS1 FS0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
NS_xxx
(MHz)
82.5
85.0
87.5
90.0
92.5
95.0
97.5
100.0
102.5
105.0
107.5
110.0
112.5
115.0
117.5
120.0
NOTE: Operation at other than the default entry is not
guaranteed. These values are for margining purposes only.
LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES
8
REVISION B 03/06/15