932SQL450 Datasheet, PDF (15/23 Pages) Integrated Device Technology – Integrated 85 ohm differential terminations

932SQL450 DATASHEET
DC Electrical Characteristics–Differential LP-HCSL Outputs
(CPU, SRC, NS_SAS, NS_SRC, DOT96)
T_A = T_COM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Slew rate
Slew rate matching
dV/dt
∆dV/dt
Scope averaging on
Slew rate matching, Scope
averaging on
MIN
TYP
MAX UNITS NOTES
1.5
2.9
4
V/ns _1,2,3
5
20
%
1,2,4
Voltage High
Voltage Low
VHigh Statistical measurement on single- 660
774
850
ended signal using oscilloscope
mV
VLow math function. (Scope averaging on) -150
83
150
Max Voltage
Min Voltage
Vswing
Vmax
Measurement on single ended
Vmin signal using absolute value. (Scope -300
918
-3
1150
mV
7
7
Vswing
Scope averaging off
300
1359
mV
1,2
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250
432
550
mV
1,5
Crossing Voltage (var) ∆-Vcross
Scope averaging off
14
140
mV
1,6
1_{Guaranteed by design and characterization, not 100% tested in production. ZO=85Ω (differential impedance).}
2 _{Measured from differential waveform}
3 _{Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window}
around differential 0V.
4 _{Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered}
on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage
thresholds the oscilloscope is to use for the edge rate calculations.
5 _{Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential}
rising edge (i.e. Clock rising and Clock# falling).
6 _{The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max}
(V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than
7 _{Includes overshoot and undershoot.}
8 _{Measured from single-ended waveform}
9 _{Measured with scope averaging off, using statistics function. Variation is difference between min and max.}
Electrical Characteristics–48MHz
T_A = 0 - 70°C; Supply Voltage V_DD/V_DDA = 3.3 V +/-5%,
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
Output High Voltage
Output Low Voltage
R_DSP
V_OH
V_OL
V_O = V_DD*(0.5)
I_OH = -1 mA
I_OL = 1 mA
Clock High Time
T_HIGH
1.5V
Clock Low Time
T_LOW
1.5V
Edge Rate
t_{slewr/f_USB}
Rising/Falling edge rate
Duty Cycle
d_t1
V_T = 1.5 V
Jitter, Cycle to cycle
t_jcyc-cyc
V_T = 1.5 V
See "Power Supply and Test Loads" page for termination circuits
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured between 0.8V and 2.0V}
MIN
12
2.4
8.094
7.694
1
45
TYP
21.7
50.4
MAX
55
0.55
10.036
9.836
2.3
55
350
UNITS
Ω
V
V
NOTES
1
ns
1
ns
1
V/ns 1,2
%
1
ps
1
REVISION B 03/06/15
15
LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES