932SQL450 Datasheet, PDF (12/23 Pages) Integrated Device Technology – Integrated 85 ohm differential terminations

932SQL450 DATASHEET
SMBus Table: NS_SAS/NS_SRC Frequency Margining Table
Byte 5 Pin #
Name
Control Function Type
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
RESERVED
Bit 4
RESERVED
Bit 3
-
FS3
Freq. Sel 3
RW
Bit 2
-
FS2
Freq. Sel 2
RW
Bit 1
-
FS1
Freq. Sel 1
RW
Bit 0
-
FS0
Freq. Sel 0
RW
0
1
See NS_SAS/NS_SRC Frequency
Table.
Default
0
0
0
0
0
1
1
1
SMBus Table: Test Mode and CPU/SRC/PCI Frequency Select Register
Byte 6 Pin #
Name
Control Function Type
0
1
Bit 7
-
Test Mode
Test Mode Type
RW
Hi-Z
REF/N
Bit 6
-
Test Select
Select Test Mode
RW
Disable
Enable
Bit 5
-
RESERVED
Bit 4
-
RESERVED
Bit 3
-
RESERVED
Bit 2
-
FS2
Freq. Sel 2
RW
See CPU/SRC/PCI Frequency
Bit 1
-
FS1
Freq. Sel 1
RW
Select Table
Bit 0
-
FS0
Freq. Sel 0
RW
Note: Internal Pull up on 100M_133M# pin will result in default CPU frequency of 100 MHz.
Default
0
0
0
1
0
0
1
1
SMBus Table: Vendor & Revision ID Register
Byte 7 Pin #
Name
Bit 7
-
RID3
Bit 6
-
RID2
Bit 5
-
RID1
Bit 4
-
RID0
Bit 3
-
VID3
Bit 2
-
VID2
Bit 1
-
VID1
Bit 0
-
VID0
Control Function
REVISION ID
(1h forB rev)
VENDOR ID
Type
R
R
R
R
R
R
R
R
0
1
1 for B rev
0001 for ICS/IDT
Default
0
0
0
1
0
0
0
1
SMBus Table: Byte Count Register
Byte 8 Pin #
Name
Bit 7
-
BC7
Bit 6
-
BC6
Bit 5
-
BC5
Bit 4
-
BC4
Bit 3
-
BC3
Bit 2
-
BC2
Bit 1
-
BC1
Bit 0
-
BC0
Control Function
Byte Count
Programming b(7:0)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Writing to this register will configure
how many bytes will be read back,
default is A bytes.
(0 to 9
Default
0
0
0
0
0
0
0
1
SMBus Table: Device ID Register
Byte 9 Pin #
Name
Bit 7
DID7
Bit 6
DID6
Bit 5
DID5
Bit 4
DID4
Bit 3
DID3
Bit 2
DID2
Bit 1
DID1
Bit 0
DID0
Control Function Type
0
R
-
R
-
R
-
Device ID
R
-
(45 hex)
R
-
R
-
R
-
R
-
1
Default
-
0
-
1
-
0
-
0
-
0
-
1
-
0
-
1
LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES
12
REVISION B 03/06/15