932SQL450 Datasheet, PDF (11/23 Pages) Integrated Device Technology – Integrated 85 ohm differential terminations

932SQL450 DATASHEET
NOTE: Pin numbers refer to TSSOP
SMBus Table: Output Enable Register
Byte 0 Pin #
Name
Bit 7
24/25
DOT96 Enable
Bit 6
50/49
NS_SAS1 Enable
Bit 5
48/47
NS_SAS0 Enable
Bit 4
44/43
NS_SRC1 Enable
Bit 3
42/41
NS_SRC0 Enable
Bit 2
36/35
SRC2 Enable
Bit 1
34/33
SRC1 Enable
Bit 0
30/31
SRC0 Enable
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable-Low/Low
Disable-Low/Low
Disable-Low/Low
Disable-Low/Low
Disable-Low/Low
Disable-Low/Low
Disable-Low/Low
Disable-Low/Low
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Default
1
1
1
1
1
1
1
1
SMBus Table: Output Enable Register
Byte 1 Pin #
Name
Bit 7
5
REF14_3x Enable
Bit 6
Bit 5
Bit 4
62/61
CPU3
Bit 3
60/59
CPU2
Bit 2
56/55
CPU1
Bit 1
54/53
CPU0
CPU/SRC/
Bit 0
PCI
Spread Spectrum Enable
Control Function Type
Output Enable
RW
RESERVED
RESERVED
Output Enable
RW
Output Enable
RW
Output Enable
RW
Output Enable
RW
Spread Off/On
RW
0
Disable-Low
Disable-Low/Low
Disable-Low/Low
Disable-Low/Low
Disable-Low/Low
Spread Off
1
Enable
Enable
Enable
Enable
Enable
Spread On
Default
1
0
0
1
1
1
1
0
SMBus Table: Output Enable Register
Byte 2 Pin #
Name
Bit 7
Bit 6
Bit 5
13
PCI4 Enable
Bit 4
14
PCI3 Enable
Bit 3
15
PCI2 Enable
Bit 2
16
PCI1 Enable
Bit 1
17
PCI0 Enable
Bit 0
21
48MHz Enable
Control Function Type
RESERVED
RESERVED
Output Enable
RW
Output Enable
RW
Output Enable
RW
Output Enable
RW
Output Enable
RW
Output Enable
RW
0
Disable-Low
Disable-Low
Disable-Low
Disable-Low
Disable-Low
Disable-Low
1
Enable
Enable
Enable
Enable
Enable
Enable
Default
0
0
1
1
1
1
1
1
SMBus Table: Differential Amplitude Control
Byte 3 Pin #
Name
Bit 7
CPU AMPLITUDE 1
Bit 6
CPU AMPLITUDE 0
Bit 5
SRC AMPLITUDE 1
Bit 4
SRC AMPLITUDE 0
Bit 3
DOT96 AMPLITUDE 1
Bit 2
DOT96 AMPLITUDE 0
Bit 1
NS-SAS/SRC AMPLITUDE 1
Bit 0
NS-SAS/SRC AMPLITUDE 0
Control Function
CPU Vhigh
SRC Vhigh
DOT96 Vhigh
NS-SAS/SRC Vhigh
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
00 = 700mV
10 = 900mV
00 = 700mV
10 = 900mV
00 = 700mV
10 = 900mV
00 = 700mV
10 = 900mV
1
01 = 800mV
11 = 1000mV
01 = 800mV
11 = 1000mV
01 = 800mV
11 = 1000mV
01 = 800mV
11 = 1000mV
Default
0
1
0
1
0
1
0
1
SMBus Table: Spread Amount Register
Byte 4 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SS AMOUNT[1]
Bit 0
SS AMOUNT[0]
Control Function Type
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Spread Amount (note RW
B1b0 must be set to '1') RW
0
00= -0.2%
01= -0.3%
1
10= -0.4%
11= -0.5%
Default
0
0
0
0
0
0
1
1
REVISION B 03/06/15
11
LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES