932SQL450 Datasheet, PDF (2/23 Pages) Integrated Device Technology – Integrated 85 ohm differential terminations

932SQL450 DATASHEET
64TSSOP Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PIN NAME
SMBCLK
GND14
AVDD14
VDD14
vREF14_2x/TEST_SELLV
GND14
GNDXTAL
X1_25
X2_25
VDDXTAL
GNDPCI
VDDPCI
PCI4_2x
PCI3_2x
PCI2_2x
PCI1_2x
PCI0_2x
GNDPCI
VDDPCI
VDD48
48M_2x
GND48
GND96
DOT96_Z85T
DOT96_Z85C
AVDD96
TEST_MODE
CKPWRGD#/PD
VDDSRC
SRC0_Z85T
SRC0_Z85C
GNDSRC
SRC1_Z85C
SRC1_Z85T
SRC2_Z85C
SRC2_Z85T
VDDSRC
AVDD_SRC
GNDSRC
NC
TYPE
DESCRIPTION
IN Clock pin of SMBUS circuitry, 5V tolerant
PWR Ground pin for 14MHz output and logic.
PWR Analog power pin for 14MHz PLL
PWR Power pin for 14MHz output and logic
14.318 MHz reference clock capable of driving 2 loads/ TEST_SEL latched input to enable test
I/O mode. The TEST_SEL input is a low threshold input. See the Electrical Tables and the Test
Clarification Table. This pin has a weak (~120Kohm) internal pull down.
PWR Ground pin for 14MHz output and logic.
PWR Ground pin for Crystal Oscillator.
IN Crystal input, Nominally 25.00MHz.
OUT Crystal output, Nominally 25.00MHz.
PWR 3.3V power for the crystal oscillator.
PWR Ground pin for PCI outputs and logic.
PWR 3.3V power for the PCI outputs and logic
OUT 3.3V PCI clock output capable of driving two loads.
OUT 3.3V PCI clock output capable of driving two loads.
OUT 3.3V PCI clock output capable of driving two loads.
OUT 3.3V PCI clock output capable of driving two loads.
OUT 3.3V PCI clock output capable of driving two loads.
PWR Ground pin for PCI outputs and logic.
PWR 3.3V power for the PCI outputs and logic
PWR 3.3V power for the 48MHz output and logic
OUT 3.3V 48MHz output capable of driving 2 loads.
PWR Ground pin for 48MHz output and logic.
PWR Ground pin for DOT96 output and logic.
OUT ^{True clock of low-power push-pull differential 96MHz output. Internally terminated to drive 85ohm}
transmission lines with no external components.
OUT ^{Complementary clock of low-power push-pull differential 96MHz output. Internally terminated to}
drive 85ohm transmission lines with no external components.
PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic
IN ^{TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test}
mode. Refer to Test Clarification Table.
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power
IN Up. PD is an asynchronous active high input pin used to put the device into a low power state.
The internal clocks and PLLs are stopped.
PWR 3.3V power for the SRC outputs and logic
OUT ^{True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm}
transmission lines with no external components.
OUT ^{Complementary clock of low-power push-pull differential SRC output. Internally terminated to}
drive 85ohm transmission lines with no external components.
PWR Ground pin for SRC outputs and logic.
OUT ^{Complementary clock of low-power push-pull differential SRC output. Internally terminated to}
drive 85ohm transmission lines with no external components.
OUT ^{True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm}
transmission lines with no external components.
OUT ^{Complementary clock of low-power push-pull differential SRC output. Internally terminated to}
drive 85ohm transmission lines with no external components.
OUT ^{True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm}
transmission lines with no external components.
PWR 3.3V power for the SRC outputs and logic
PWR 3.3V power for the SRC PLL analog circuits
PWR Ground pin for SRC outputs and logic.
N/A No Connection.
LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES
2
REVISION B 03/06/15