932SQL450 Datasheet, PDF (3/23 Pages) Integrated Device Technology – Integrated 85 ohm differential terminations

932SQL450 DATASHEET
64TSSOP Pin Descriptions (cont.)
PIN #
PIN NAME
41 NS_SRC0_Z85C
42 NS_SRC0_Z85T
43 NS_SRC1_Z85C
44 NS_SRC1_Z85T
45 VDDNS
46 GNDNS
47 NS_SAS0_Z85C
48 NS_SAS0_Z85T
49 NS_SAS1_Z85C
50 NS_SAS1_Z85T
51 AVDD_NS_SAS
52 GNDNS
53 CPU0_Z85C
54 CPU0_Z85T
55 CPU1_Z85C
56 CPU1_Z85T
57 VDDCPU
58 GNDCPU
59 _{CPU2_Z85C}
60 CPU2_Z85T
61 CPU3_Z85C
62 CPU3_Z85T
63 VDDCPU
64 SMBDAT
TYPE
DESCRIPTION
OUT ^{Complementary clock of low-power push-pull differential non-spreading SRC output. Internally}
terminated to drive 85ohm transmission lines with no external components.
OUT ^{True clock of low-power push-pull differential non-spreading SRC output. Internally terminated to}
drive 85ohm transmission lines with no external components.
OUT
Complementary clock of low-power push-pull differential non-spreading SRC output. Internally
terminated to drive 85ohm transmission lines with no external components.
OUT ^{True clock of low-power push-pull differential non-spreading SRC output. Internally terminated to}
drive 85ohm transmission lines with no external components.
PWR 3.3V power for the Non-Spreading differential outputs outputs and logic
PWR Ground pin for non-spreading differential outputs and logic.
OUT ^{Complementary clock of low-power push-pull differential non-spreading SAS output. Internally}
terminated to drive 85ohm transmission lines with no external components.
OUT ^{True clock of low-power push-pull differential non-spreading SAS output. Internally terminated to}
drive 85ohm transmission lines with no external components.
OUT ^{Complementary clock of low-power push-pull differential non-spreading SAS output. Internally}
terminated to drive 85ohm transmission lines with no external components.
OUT ^{True clock of low-power push-pull differential non-spreading SAS output. Internally terminated to}
drive 85ohm transmission lines with no external components.
PWR 3.3V power for the non-spreading SAS/SRC PLL analog circuits.
PWR Ground pin for non-spreading differential outputs and logic.
OUT ^{Complementary clock of low-power push-pull differential CPU output. Internally terminated to}
drive 85ohm transmission lines with no external components.
OUT ^{True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm}
transmission lines with no external components.
OUT
Complementary clock of low-power push-pull differential CPU output.
drive 85ohm transmission lines with no external components.
Internally terminated to
OUT ^{True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm}
transmission lines with no external components.
PWR 3.3V power for the CPU outputs and logic
PWR Ground pin for CPU outputs and logic.
OUT
Complementary clock of low-power push-pull differential CPU output.
drive 85ohm transmission lines with no external components.
Internally terminated to
OUT ^{True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm}
transmission lines with no external components.
OUT ^{Complementary clock of low-power push-pull differential CPU output. Internally terminated to}
drive 85ohm transmission lines with no external components.
OUT ^{True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm}
transmission lines with no external components.
PWR 3.3V power for the CPU outputs and logic
I/O Data pin of SMBUS circuitry, 5V tolerant
REVISION B 03/06/15
3
LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES