932SQL450 Datasheet, PDF (16/23 Pages) Integrated Device Technology – Integrated 85 ohm differential terminations

932SQL450 DATASHEET
Electrical Characteristics–Phase Jitter Parameters
T_A = 0 - 70°C; Supply Voltage V_DD/V_DDA = 3.3 V +/-5%,
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX ^INDUST. UNITS Notes
LIMIT
t_jphPCIeG1
PCIe Gen 1
35
39
86
ps (p-p)
1,2,3,
6
t_jphPCIeG2
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
1.52
1.84
2.19
2.42
3
ps _1,2,6
(rms)
3.1
ps _1,2,6
(rms)
Phase Jitter
t_jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR =
10MHz)
0.51
0.59
1
ps 1,2,4,
(rms) 6
QPI & SMI
(100MHz, 4.8Gb/s, 6.4Gb/s 12UI)
0.25
0.37
0.5
ps _1,5,7
(rms)
t_{jphQPI_SMI}
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
0.18
0.23
0.3
ps _1,5,7
(rms)
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
0.15
0.19
0.2
ps
(rms)
1,5,7
t_jphSAS12G
SAS 12G
1.15
1.27
ps
1.3
(rms) ^1,5,8
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{See http://www.pcisig.com for complete specs}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.}
4 _{Subject to final radification by PCI SIG.}
5 _{Calculated from Intel-supplied Clock Jitter Tool v 1.6.6}
6 _{Applied to SRC outputs}
7 _{Applies to CPU outputs}
8 _{Applies to NS_SAS, NS_SRC outputs, Spread Off}
Electrical Characteristics–PCI
T_A = 0 - 70°C; Supply Voltage V_DD/V_DDA = 3.3 V +/-5%,
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
R_DSP
V_O = V_DD*(0.5)
Output High Voltage
V_OH
I_OH = -1 mA
Output Low Voltage
V_OL
I_OL = 1 mA
Clock High Time
T_HIGH
1.5V
MIN
TYP
MAX UNITS NOTES
12
22
55
Ω
1
2.4
V
0.55
V
12
ns
1
Clock Low Time
T_LOW
1.5V
12
ns
1
Edge Rate
t_slewr/f
Rising/Falling edge rate
1
1.7
4
V/ns
1,2
Duty Cycle
d_t1
V_T = 1.5 V
45
50.4
55
%
1
Group Skew
t_skew
V_T = 1.5 V
197
500
ps
1
Jitter, Cycle to cycle
t_jcyc-cyc
V_T = 1.5 V
45.52
500
ps
1
See "Power Supply and Test Loads" page for termination circuits
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured between 0.8V and 2.0V}
LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES
16
REVISION B 03/06/15