70V25L25PFI Datasheet, PDF (8/25 Pages) Integrated Device Technology – True Dual-Ported memory cells which allow simultaneous reads of the same memory location

IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V35/34⁽¹⁾ (VDD = 3.3V ± 0.3V)
Symbol
Parameter
Test Condition
Version
70V35/34X15
Com'l Only
70V35/34X20
Com'l
& Ind
70V35/34X25
Com'l Only
Typ.⁽²⁾ Max. Typ.⁽²⁾ Max. Typ.⁽²⁾ Max. Unit
IDD Dynamic Operating
Current
(Both Ports Active)
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX⁽³⁾
COM'L
IND
S 150 215 140 200 130 190 mA
L 140 185 130 175 125 165
S
____
____
140 225
____
____
L
____
____
130
195
____
____
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CER and CEL = VIH
SEMR = SEML = VIH
f = fMAX⁽³⁾
COM'L
S 25
35
20
30
16
30 mA
L
20
30
15
25
13
25
MIL &
IND
S
____
____
20
45
____
____
L
____
____
15
40
____
____
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH⁽⁵⁾
Active Port Outputs Disabled,
f=fMAX⁽³⁾
SEMR = SEML = VIH
COM'L
S 85
120
80
110
75
110 mA
L
80
110
75
100
72
95
MIL &
IND
S
____
____
80
130
____
____
L
____
____
75
115
____
____
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CEL and
CER > VDD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0⁽⁴⁾
SEMR = SEML > VDD - 0.2V
COM'L
S 1.0
5
1.0
5
1.0
5 mA
L 0.2
2.5
0.2
2.5
0.2
2.5
MIL &
IND
S
____
____
1.0
15
____
____
L
____
____
0.2
5
____
____
ISB4 Full Standby Current
(One Port -
CMOS Level Inputs)
CE"A" < 0.2V and
CE"B" > VDD - 0.2V⁽⁵⁾
SEMR = SEML > VDD - 0.2V
VIN > VDD - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
f = fMAX⁽³⁾
COM'L
S 85
125
80
115
75
105 mA
L
80
105
75
100
70
90
MIL &
IND
S
____
____
80
130
____
____
L
____
____
75
115
____
____
NOTES:
5624 tbl 09
1. 'X' in part number indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 115mA (typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
5624 tbl 10
Timing of Power-Up Power-Down
3.3V
3.3V
DATAOUT
BUSY
INT
435Ω
590Ω
DATAOUT
30pF
435Ω
590Ω
5pF*
Figure 1. AC Output Test Load
,
5624 drw 06
Figure 2. Output Test
Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
CE
tPU
ICC
50%
ISB
tPD
50%
5624 drw 07 ^,
6.482