70V25L25PFI Datasheet, PDF (13/25 Pages) Integrated Device Technology – True Dual-Ported memory cells which allow simultaneous reads of the same memory location

IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage for 70V25/24 ⁽⁵⁾
70V25/24X15
Com'l Only
70V25/24X20
Com'l
& Ind
70V25/24X25
Com'l
& Ind
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
tWC
Write Cycle Time
tEW
Chip Enable to End-of-Write⁽³⁾
15
____
20
____
25
____
ns
12
____
15
____
20
____
ns
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time⁽³⁾
12
____
15
____
20
____
ns
0
____
0
____
0
____
ns
tWP
Write Pulse Width
12
____
15
____
20
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
tHZ
Output High-Z Time^(1,2)
tDH
Data Hold Time⁽⁴⁾
tWZ
Write Enable to Output in High-Z^(1,2)
tOW
Output Active from End-of-Write^(1,2,4)
10
____
15
____
15
____
ns
____
10
____
12
____
15
ns
0
____
0
____
0
____
ns
____
10
____
12
____
15
ns
0
____
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
5624 tbl 12a
70V25/24X35
Com'l Only
70V25/24X55
Com'l Only
Symbol
Parameter
Min. Max. Min. Max. Unit
WRITE CYCLE
tWC
Write Cycle Time
35
____
55
____
ns
tEW
Chip Enable to End-of-Write⁽³⁾
30
____
45
____
ns
tAW
Address Valid to End-of-Write
30
____
45
____
ns
tAS
Address Set-up Time⁽³⁾
0
____
0
____
ns
tWP
Write Pulse Width
25
____
40
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
tHZ
Output High-Z Time^(1,2)
tDH
Data Hold Time⁽⁴⁾
tWZ
Write Enable to Output in High-Z^(1,2)
tOW
Output Active from End-of-Write^(1,2,4)
15
____
30
____
ns
____
15
____
25
ns
0
____
0
____
ns
____
15
____
25
ns
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
ns
NOTES:
5624 tbl 12b
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for
the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
61.432