70V25L25PFI Datasheet, PDF (15/25 Pages) Integrated Device Technology – True Dual-Ported memory cells which allow simultaneous reads of the same memory location

IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾
tOH
tSAA
A0-A2
SEM
I/O0
R/W
VALID ADDRESS
tAW
tWR
tEW
tDW
DATAIN
VALID
tAS
tWP
tDH
VALID ADDRESS
tACE
tSOP
DATAOUT
VALID⁽²⁾
tSWRD
tAOE
OE
Write Cycle
Read Cycle
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24) equal to the semaphore value.
5624 drw 11
Timing Waveform of Semaphore Write Contention^(1,3,4)
A0"A"-A2"A"
MATCH
SIDE⁽²⁾ _"A"
R/W"A"
SEM"A"
A0"B"-A2"B"
SIDE⁽²⁾ "B"
R/W"B"
tSPS
MATCH
SEM"B"
5624 drw 12 ^,
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
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