70V25L25PFI Datasheet, PDF (22/25 Pages) Integrated Device Technology – True Dual-Ported memory cells which allow simultaneous reads of the same memory location

IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
MASTER
Dual Port
SRAM
BUSYL
CE
BUSYR
Industrial and Commercial Temperature Ranges
SLAVE
CE
Dual Port
SRAM
BUSYL ^BUSYR
BUSYL
MASTER
CE
Dual Port
SRAM
BUSYL BUSYR
SLAVE
CE
Dual Port
SRAM
BUSYL BUSYR
BUSYR
,
5624 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V35/34 (IDT70V25/24) SRAMs.
Functional Description
The IDT70V35/34 (IDT70V25/24) provides two ports with separate
control, address and I/O pins that permit independent access for reads or
writes to any location in memory. The IDT70V35/34 (IDT70V25/24) has
an automatic power down feature controlled by CE. The CE controls on-
chip power down circuitry that permits the respective port to go into a
standby mode when not selected (CE HIGH). When a port is enabled,
access to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 1FFE
(HEX) (FFE for IDT70V34 and IDT70V24), where a write is defined as
theCER= R/WR= VIL per Truth Table III. The left port clears the interrupt
on the IDT70V35 and IDT70V25 by an address location 1FFE (FFE for
IDT70V34 and IDT70V24) access when CEL = OEL = VIL, R/WL is a "don't
care". Likewise, the right port interrupt flag (INTR) is set when the left port
writes to memory location 1FFF for IDT70V35 and IDT70V25 (HEX) (FFF
for IDT70V34 and IDT70V24) and to clear the interrupt flag (INTR), the
right port must read the memory location 1FFF for IDT70V35 and
IDT70V25 (FFF for IDT70V34 and IDT70V24). The message (16 bits)
at 1FFE or 1FFF for IDT70V35 and IDT70V25 (FFE or FFF for
IDT70V34 and IDT70V24) is user-defined, since it is an addressable
SRAM location. If the interrupt function is not used, address locations 1FFE
and 1FFF for IDT70V35 and IDT70V25 (FFE and FFF for IDT70V34 and
IDT70V24) are not used as mail boxes, but as part of the random access
memory. Refer to Truth Table III for the interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the SRAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the SRAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70V35/34 (IDT70V25/24) SRAM in
master mode, are push-pull type outputs and do not require pull up
resistors to operate. If these SRAMs are being expanded in depth, then
the BUSY indication for the resulting array requires the use of an external
AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V35/34 (IDT70V25/24) SRAM array in
width while using BUSY logic, one master part is used to decide which side
of the SRAM array will receive a BUSY indication, and to output that
indication. Any number of slaves to be addressed in the same address
range as the master, use the BUSY signal as a write inhibit signal. Thus
on the IDT70V35/34 (IDT70V25/24) SRAM the BUSY pin is an output if
the part is used as a master (M/S pin = VIH), and the BUSY pin is an input
if the part used as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Semaphores
The IDT70V35/34 (IDT70V25/24) is an extremely fast Dual-Port 8/
4K x 18 (8/4K x 16) CMOS Static RAM with an additional 8 address
locations dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port SRAM to claim a privilege
over the other processor for functions defined by the system designer’s
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