70V25L25PFI Datasheet, PDF (21/25 Pages) Integrated Device Technology – True Dual-Ported memory cells which allow simultaneous reads of the same memory location

IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Truth Table III — Interrupt Flag⁽¹⁾
Left Port
R/WL
CEL
OEL
A12L-A0L⁽⁴⁾
INTL
R/WR
L
L
X
1FFF⁽⁴⁾
X
X
X
X
X
X
X
X
X
X
X
X
L⁽³⁾
L
X
L
L
1FFE⁽⁴⁾
H⁽²⁾
X
Industrial and Commercial Temperature Ranges
Right Port
CER
OER
A12R-A0R⁽⁴⁾
INTR
Function
X
X
X
L⁽²⁾ Set Right INTR Flag
L
L
1FFF⁽⁴⁾
H⁽³⁾ Reset Right INTR Flag
L
X
1FFE⁽⁴⁾
X Set Left INTL Flag
X
X
X
X Reset Left INTL Flag
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. A12 is a NC for IDT70V34 and for IDT70V24, therefore Interrupt Addresses are FFF and FFE.
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
CEL CER
A12L-A0L⁽⁴⁾
A12R-A0R
BUSYL⁽¹⁾ BUSYR⁽¹⁾
Function
5624 tbl 15
X X NO MATCH
H
H
Normal
HX
MATCH
H
H
Normal
XH
MATCH
H
H
Normal
LL
MATCH
Note⁽²⁾
Note⁽²⁾ Write Inhibit⁽³⁾
NOTES:
5624 tbl 16
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70V35/34 (IDT70V25/24) are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A12 is a NC for IDT70V34 and for IDT70V24. Address comparison will be for A0 - A11.
Truth Table V — Example of Semaphore Procurement Sequence^(1,2,3)
Functions
D0 - D17 Left⁽²⁾
D0 - D17 Right⁽²⁾
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
5624 tbl 17
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V35/34 (IDT70V25/24).
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24). These eight semaphores
are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Tables.
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