70V25L25PFI Datasheet, PDF (4/25 Pages) Integrated Device Technology – True Dual-Ported memory cells which allow simultaneous reads of the same memory location

IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Pin Configurations^(1,2,3,4)(con't)
Industrial and Commercial Temperature Ranges
06/11/04
63
61
60
58
55
54
11 _{I/O7L I/O5L I/O4L I/O2L I/O0L OEL}
51
48
SEML LBL
46
A11L
45
A10L
42
A7L
66
64
62
59
56
49
10 _{I/O10L I/O8L I/O6L I/O3L I/O1L UBL}
50
CEL
47
44
A12L(1) A9L
43
A8L
40
A5L
67
65
09 _{I/O11L I/O9L}
57
VSS
53
VDD
52
R/WL
41
A6L
39
A4L
69
68
08 _{I/O13L I/O12L}
38
A3L
37
A2L
72
71
73
07 _{I/O15L I/O14L VDD}
75
70
06 _{I/O0R VSS}
74
VSS
76
77
78
05 _{I/O1R I/O2R VDD}
IDT70V25/24
G
G84-3⁽⁴⁾
84-Pin PGA
Top View⁽⁵⁾
33
35
BUSYL A0L
34
INTL
32
VSS
31
M/S
36
A1L
28
A0R
29
INTR
30
BUSYR
79
80
04 _{I/O3R I/O4R}
26
A2R
27
A1R
81
83
03 _{I/O5R I/O7R}
7
VSS
11
VSS
12
SEMR
23
A5R
25
A3R
82
1
2
5
8
10
14
02 _{I/O6R I/O9R I/O10R I/O13R I/O15R R/WR UBR}
17
A11R
20
A8R
22
A6R
24
A4R
84
3
4
6
9
15
01 _{I/O8R I/O11R I/O12R I/O14R OER LBR}
13
CER
16
18
A12R(1) A10R
19
A9R
21
A7R
A
B
C
D
E
F
G
H
J
K
L
Index
5624 drw 04
NOTES:
1. A12 is a NC for IDT70V24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. G84-3 package body is approximately 1.12 in x 1.12 in x .16 in.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42