70V25L25PFI Datasheet, PDF (20/25 Pages) Integrated Device Technology – True Dual-Ported memory cells which allow simultaneous reads of the same memory location

IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Waveform of Interrupt Timing⁽¹⁾
ADDR"A"
CE"A"
tAS⁽³⁾
tWC
INTERRUPT SET ADDRESS ⁽²⁾
Industrial and Commercial Temperature Ranges
tWR⁽⁴⁾
R/W"A"
INT"B"
tINS ⁽³⁾
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ADDR"B"
CE"B"
tAS⁽³⁾
tRC
INTERRUPT CLEAR ADDRESS ⁽²⁾
OE"B"
INT"B"
tINR⁽³⁾
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
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6.2402