STAC9752 Datasheet, PDF (61/95 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
8.1.20.
Extended Audio Control/Status (2Ah)
Default: 0400h* (*default depends on CODEC ID)
D15
D14
VCFG
D7
D6
RESERVED
D13
D12
RESERVED
D5
D4
SPSA1
SPSA0
D11
D3
RSRVD
D10
SPCV
D2
SPDIF
D9
D8
RESERVED
D1
D0
RSRVD VRA enable
Note: If pin 48 is held high at powerup, the SPDIF is not available and bits D15:D1 can not be written and will
read back zero.
Pin 48: To Enable SPDIF, use an external 1KΩ - 1 0 KΩ pulldown resistor. To Disable SPDIF, use an
external 1KΩ - 1 0 KΩ pullup resistor. Do NOT leave Pin 48 floating.
Bit(s) Reset Value
15
14-11
10
0
9:6
0
Name
VCFG
Reserved
SPCV
Reserved
Description
Determines the SPDIF transmitter behavior when data is not being
transmitted. When asserted, this bit forces the deassertion of the SPDIF
“Validity” flag, which is bit 28 transmitted by the SPDIF sub-frame. The “V” bit
is defined in the SPDIF Control Register (Reg 3Ah).
If “V” = 1 and “VCFG” = 0, then for each S/PDIF sub-frame (Left & Right),
bit[28] “Validity” flag reflects whether or not an internal CODEC transmission
error has occurred. Specifically an internal CODEC error should result in the
“Validity” flag being set to 1.
If “V” = 0 and “VCFG” = 1, In the case where the S/PDIF transmitter does not
receive a valid sample from the AC'97 controller, (Left or Right), the S/PDIF
transmitter should set the “Validity” flag to “0” and pad the “Audio Sample
Word” with “0”s for sub-frame in question. If a valid sample (Left or Right) was
received and successfully transmitted, the “Validity” flag should be “0” for that
sub-frame.
Default state, coming out of reset, for “V” and “VCFG” should be 0 and 0.
These bits can be set via driver .inf options.
Reserved
0 = Invalid SPDIF configuration
1 = Valid SPDIF configuration
Bit not used, should read back 0
SPDIF slot assignment
If CID[1:0] = 00 then SPSA[1:0] resets to 01
If CID[1:0] = 01 then SPSA[1:0] resets to 10
If CID[1:0] = 10 then SPSA[1:0] resets to 10
5:4
0
SPSA1:SPSA0 If CID[1:0] = 11 then SPSA[1:0] resets to 11
3
2
0
Reserved
SPDIF
00 = left slot 3, right slot 4
01 = left slot 7, right slot 8
10 = left slot 6, right slot 9
11 = left slot 10, right slot 11
Reserved
0 = Disables SPDIF (SPDIF_OUT is high Z) (note 1)
1 = Enable SPDIF
SPDIF is a control register for Reg 3Ah, this bit must be set low i.e. SPDIF
disabled in order to write to Reg 3Ah Bits D15,D13:D0.
IDT™
61
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
REV 3.3 1206