STAC9752 Datasheet, PDF (60/95 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
The Extended Audio ID register is a read only register except for bits D4 and D5. ID1 and ID0 echo
the configuration of the CODEC as defined by the programming of pins 45 and 46 externally. The
primary CODEC returns “00”, while any other code identifies the CODEC as one of three secondary
CODEC possibilities. The AMAP bit, D9, will return a 1 indicating that the CODEC supports the
optional “AC’97 2.3 compliant AC-Link slot to audio DAC mappings”.The default condition assumes
that 0 is loaded into the DSA0 and DSA1 bits of the Extended Audio ID (Index 28h). With 0 in the
DSA1 and DSA0 bits, the CODEC slot assignments are as per the AC’97 specification recommen-
dations. If the DSA1 and DSA0 bits do not contain 0, the slot assignments are as per the table in the
section describing the Extended Audio ID (Index 28h). The VRA bit, D0, will return a 1 indicating that
the CODEC supports the optional variable sample rate conversion as defined by the AC’97 specifi-
cation.
Table 18. Extended Audio ID Register Functions
Bit
Name
Access
15:14
ID [1,0]
Read only
13:12
11:10
9:6
RESERVED
REV[1:0]
RSVD
Read only
Read only
Read only
Reset Value
variable
00
10
0
00
Function
0,0 = XTAL_OUT grounded (Note 1)
CID1#, CID0# = XTAL_OUT crystal or floating
Bits not used, should read back 00
Indicates CODEC is AC’97 Rev 2.3 compliant
Reserved
DAC slot assignment
5:4
DSA [1,0] Read/Write
If CID[1:0] = 00 then DSA[1:0] resets to 00
If CID[1:0] = 01 then DSA[1:0] resets to 01
If CID[1:0] = 10 then DSA[1:0] resets to 01
If CID[1:0] = 11 then DSA[1:0] resets to 10
00 = left slot 3, right slot 4
01 = left slot 7, right slot 8
10 = left slot 6, right slot 9
11 = left slot 10, right slot 11
3
RSVD
Read only
0
RESERVED
2
SPDIF
Read only
1
0 = SPDIF pulled high on reset, SPDIF disabled
1 = default, SPDIF enabled (Note 2)
1
RSVD
Read only
0
RESERVED
0
VRA
Read only
1
Variable sample rates supported (Always = 1)
1. External CID pin status (from analog) these bits are the logical inversion of the pin polarity (pin 45-46).
These bits are zero if XTAL_OUT is grounded with an alternate external clock source in primary mode
only. Secondary mode can either be through BIT CLK driven or 24MHz clock driver, with XTAL_OUT
floating.
2. If pin 48 is held high at powerup, this bit will be held to zero, to indicate the SPDIF is not available.
Pin 48: To Enable SPDIF, use an external 1KΩ - 1 0 KΩ pulldown resistor. To Disable SPDIF, use an
external 1KΩ - 1 0 KΩ pullup resistor. Do NOT leave Pin 48 floating.
IDT™
60
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
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