STAC9752 Datasheet, PDF (24/95 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
Figure 12. CODEC Clock Source Detection
AC'97 Clock Source
Detection
RESET# Signal Asserted
BIT_CLK Toggling?
No
After RESET# Signal
Deasserted
Yes
12.288MHz signal on BIT_CLK is
being generated externally; codec
uses this signal as the clock.
24.576MHz
crystal present?
No
24.576MHz
oscillator present?
No
14.318MHz
oscillator presnent?
No
Error condition - no clock
source present
Yes
Yes
Yes
24.576MHz Crystal on XTL_IN
and XTL_OUT used by codec to
generate clock on BIT_CLK
24.576 MHz signal on XTL_IN
used by codec to generate
12.288MHz clock on BIT_CLK
14.318 MHz signal on XTL_IN
used by codec to generate
12.288MHz clock on BIT_CLK
The STAC9752/9753 uses the XTAL_OUT Pin (Pin 3) and the CID0 and CID1 pins (Pins 45 & 46) to
determine its alternate clock frequencies. See section 2.2.4: page17 for additional information on
Crystal Elimination and for supported clock frequencies.
If, when the RESET# signal has been de-asserted, the CODEC has not detected a signal on
BIT_CLK as defined in the previous paragraph, then the AC‘97 CODEC derives its clock internally
from an externally attached 24.576 MHz crystal or oscillator, or optionally from an external
14.31 MHz oscillator, and drives a buffered 12.288 MHz clock to its digital companion Controller
over AC-Link under the signal name “BIT_CLK”. Clock jitter at the DACs and ADCs is a fundamental
impediment to high quality output, and the internally generated clock will provide AC‘97 with a clean
clock that is independent of the physical proximity of AC‘97’s companion Digital Controller (hence-
forth referred to as “the Controller”).
If BIT_CLK begins toggling while the RESET# signal is still asserted, the clock is being provided by
other than the primary CODEC, for instance by the controller or by a discrete clock source. In this
case, the primary CODEC must act as a consumer of the BIT_CLK signal as if it were a secondary
CODEC.
The beginning of all audio sample packets, or Audio Frames, transferred over AC-Link is synchro-
nized to the rising edge of the SYNC signal. SYNC is driven by the Controller. The Controller gener-
IDT™
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STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
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