STAC9752 Datasheet, PDF (58/95 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
Bit(s) Reset Value Access
Name
Description
Interrupt Enable
0 = Interrupt generation is masked.
1 = Interrupt generation is un-masked.
The driver should not un-mask the interrupt unless ensured by the
11
0
Read / Write
I0
AC ‘97 controller that no conflict is possible with modem slot 12 -
GPI functionality. Some AC’97 2.2 compliant controllers will not
likely support audio CODEC interrupt infrastructure. In either case,
S/W should poll the interrupt status after initiating a sense cycle
and wait for Sense Cycle Max Delay to determine if an interrupting
event has occurred.
10:4
0
Read Only RESERVED Bits not used, should read back 0
Page Selector
0h = Vendor Specific
1h = Page ID 01 (See Section 8.4 for additional information on the
Paging Registers)
Fh = Reserved Pages
This register is used to select a descriptor of 16 word pages
3:0
0
Read / Write
PG3:PG0
between registers 60h to 6Fh. Value 0h is used to select vendor
specific space to maintain compatibility with AC’97 2.2 vendor
specific registers.
System S/W determines implemented pages by writing the page
number and reading the value back. All implemented pages must
be consecutive. (i.e., page 2h cannot be implemented without page
1h).
These registers are NOT reset on RESET#.
8.1.18.
Powerdown Ctrl/Stat (26h)
Default: 000Fh
D15
D14
D13
D12
D11
D10
D9
D8
EAPD
PR6
PR5
PR4
PR3
PR2
PR1
PR0
D7
D6
D5
D4
D3
D2
D1
D0
RESERVED
REF
ANL
DAC
ADC
Bit(s) Reset Value
15
0
14
0
13
0
12
0
11
0
10
0
9
0
Name
EAPD
PR6
PR5
PR4
PR3
PR2
PR1
Description
1 = Forces EAPD pad to Vdd
0 = Forces EAPD pad to GND
0 = Headphone Amp powered up
1 = Headphone Amp powered down
0 = Digital Clk active
1 = Digital Clk disable.
0 = digital active
1 = Powerdown: PLL, AC-Link, Xtal oscillator ;
0 = VREF and VREFOUT are active
1 = VREF and VREFOUT are powered down, and PR2 is asserted in
analog block
0 = analog active
1 = all signal path analog is powered down
0 = DAC powered up
1 = DAC powered down
IDT™
58
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
REV 3.3 1206