STAC9752 Datasheet, PDF (28/95 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
4.6.3.
4.6.2.2. CODEC Initiates Wake-up
The STAC9752/9753 (running off Vaux) can trigger a wake event (PME#) by transitioning
SDATA_IN from low to high and holding it high until either a warm or cold reset is observed on the
AC-Link. This functionality is typically implemented in modem CODECs that detect ring, Caller ID,
etc.
Note that when the AC-Link is either programmed to the low power mode or shut off completely,
BIT_CLK may stop if the primary CODEC is supplying the clock, which shuts down the AC-Link
clock to the Secondary CODEC¹. In order for a Secondary CODEC to react to an external event
(phone ringing), it must support an independent clocking scheme for any PME# associated logic that
must be kept alive when the AC-Link is down. This includes logic to asynchronously drive
SDATA_IN to a logic high-level which signals a wake request to the AC‘97 Digital Controller.
CODEC Reset
There are three types of AC‘97 reset:
• a cold reset where all AC‘97 logic (most registers included) is initialized to its default state
• a warm reset where the contents of the AC‘97 register set are left unaltered
• a register reset which only initializes the AC‘97 registers to their default states
4.6.3.1. Cold AC‘97 Reset
A cold reset is achieved by asserting RESET# (low) for the minimum specified time, then subse-
quently de-asserting RESET# (high). BIT_CLK and SDATA_IN will be activated, or re-activated as
the case may be, and all AC‘97 control registers will be initialized to their default power on reset val-
ues.
RESET# is an asynchronous AC‘97 input.
4.6.3.2. Warm AC‘97 Reset
A warm AC‘97 reset will re-activate the AC-Link without altering the current AC‘97 register values. A
warm reset is signaled by driving SYNC high for a minimum of 1 µs in the absence of BIT_CLK.
Within normal audio frames, SYNC is a synchronous AC‘97 input. However, in the absence of
BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to
AC‘97.
AC‘97 MUST NOT respond with the activation of BIT_CLK until SYNC has been sampled low again
by AC‘97. This will preclude the false detection of a new audio frame.
4.6.3.3. Register AC‘97 Reset
Most registers in an AC device can be restored to their default values by performing a write (any
value) to the Reset Register, 00h.
1.
Secondary CODECs always configure the BIT_CLK pin as an input.
IDT™
28
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
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