90E32 Datasheet, PDF (54/71 Pages) Integrated Device Technology – Poly-Phase High-Performance Wide-Span Energy Metering IC

90E32
POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Table-6 Calibration Registers
Register
Address
Register Name
Read/Write
Type
Functional Description
Power-on Value
4AH
PhiB
R/W
Phase B calibration phase angle
0000H
4BH
GainC
R/W
Phase C Active/Reactive Energy calibration
gain
0000H
4CH
PhiC
R/W
Phase C calibration phase angle
0000H
4DH
CS1^*
R/W
Checksum 1
0000H
Note: The calculation of the CS1 register is similar as the CS0 register by calculating the 41H-4CH registers. For details, please refer to IDT application note AN-644.
PoffsetA
Phase A Active Power Offset
Address: 41H
Type: Read/Write
Default Value: 0000H
Bit
Name
15-0
Offset
Power offset. Signed 16-bit integer.
Description
QoffsetA
Phase A Reactive Power Offset
Address: 42H
Type: Read/Write
Default Value: 0000H
Bit
Name
15-0
Offset
Power offset. Signed 16-bit integer.
Description
GainA
Phase A Active/Reactive Energy calibration gain
Address: 47H
Type: Read/Write
Default Value: 0000H
Bit
Name
15-0
Gain
Energy calibration gain.
Signed integer.
Actual power gain = (1+ Gain)
Description
PhiA
Phase A calibration phase angle
Address: 48H
Type: Read/Write
Default Value: 0000H
Bit
Name
15
DelayV
14:10
9:0
-
DelayCycles
Description
0: Delay Cycles are applied to current channel. (default)
1: Delay Cycles are applied to voltage channel.
Reserved.
Unit is 2.048MHz cycle. It is an unsigned 10 bit integer.
The phase B and phase C’s calibration registers are similar as phase A.
Register
54
December 9, 2011