90E32 Datasheet, PDF (12/71 Pages) Integrated Device Technology – Poly-Phase High-Performance Wide-Span Energy Metering IC

90E32
POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
3
FUNCTION DESCRIPTION
3.1 POWER SUPPLY
The 90E32 works with single power rail 3.3V. An on-chip voltage reg-
ulator regulates the 1.8V voltage for the digital logic.
The regulated 1.8V power is connected to the VDD18 pin. It needs to
be bypassed by an external capacitor.
The 90E32 has multiple power modes, in Idle and Detection modes
the 1.8V power regulator is not turned on and the digital logic is not pow-
ered. When the logic is not powered, all the configured register values
are not kept (all context lost) except for Detection mode related registers
(10H~13H) for Detection mode configuration.
User has to re-configure the registers in Partial Measurement mode
or Normal mode when transiting from Idle or Detection mode. Refer to
3.6 Power Mode for power mode details.
3.2 CLOCK
The 90E32 has an on-chip oscillator and can directly connect to an
external crystal.
The OSCI pin can also be driven with a clock source.
The oscillator will be powered down in Idle and Detection power
modes, as described in 3.6 Power Mode.
3.3 RESET
There are three reset sources for the 90E32:
- RESET pin
- On-chip Power On Reset circuit
- Software Reset generated by the Software Reset register
3.3.1
RESET PIN
The RESET pin can be asserted to reset the 90E32. The RESET pin
has RC filter with typical time constant of 2µs in the I/O, as well as a 2µs
(typical) de-glitch filter.
Any reset pulse that is shorter than 2µs can not reset the 90E32.
3.3.2 POWER ON RESET (POR)
The POR circuit resets the 90E32 at power up.
POR circuit triggers reset when:
- DVDD power up, crossing the power-up threshold. Refer to Fig-
ure-19.
- VDD18 regulator changing from disable to enable, i.e. from Idle or
Detection mode to Partial Measurement mode or Normal mode.
Refer to Figure-18.
3.3.3 SOFTWARE RESET
Chip reset can be triggered by writing to the SoftReset register in
Normal mode. The software reset is the same as the reset scope gener-
ated from the RESET pin or POR.
These three reset sources have the same reset scope.
All digital logics and registers, except for the Harmonic Ratio regis-
ters will be subject to reset.
• Interface logic: clock dividers
• Digital core/ logic: All registers except for some other special
registers, refer to 6.3.1 Detection Mode Registers.
Function Description
12
December 9, 2011