90E32 Datasheet, PDF (27/71 Pages) Integrated Device Technology – Poly-Phase High-Performance Wide-Span Energy Metering IC

90E32
POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
4.2 SPI INTERFACE
The interface works in slave mode as shown in Figure-11.
4.2.1 SPI SLAVE INTERFACE FORMAT
In the SPI mode, data on SDI is shifted into the chip on the rising
edge of SCLK while data on SDO is shifted out of the chip on the falling
edge of SCLK.
Refer to Figure-12 and Figure-13 below for the timing diagram.
Access type:
The first bit on SDI defines the access type as below:
Read Sequence:
Instruction
Read
Write
Description
read from registers
write to registers
Instruction Format
1
0
Address:
Fixed 15-bit, following the access type bits. The lower 10-bit is
decoded as address; the higher 5 bits are ‘Don't Care’.
Read/Write data:
Fixed as 16 bits.
CS
SCLK
SDI
SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Register Address
X X X X X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Don't care
High Impedance
16-bit data
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Write Sequence:
Figure-12 Read Sequence
CS
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Register Address
16-bit data
SDI
X X X X X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
High Impedance
Figure-13 Write Sequence
4.2.2 RELIABILITY ENHANCEMENT FEATURE
The SPI read/write transaction is CS-low defined. Each transaction
can only access one register.
Within each CS-low defined transaction:
Write: access occurs only when CS goes from low to high and there
are exactly 32 SCLK cycles received during CS low period.
Read: if SCLK>=16 (full address received), data is read out from
internal registers and gets to the SDO pin; and the LastSPIData register
is updated. The R/C registers can only be cleared after the LastSPIData
register is updated.
SPI Interface
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December 9, 2011