90E32 Datasheet, PDF (41/71 Pages) Integrated Device Technology – Poly-Phase High-Performance Wide-Span Energy Metering IC

90E32
POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
13-12
11
10
9-8
7
6
5
4
3
2
1
0
-
THDUOvEn
THDIOvEn
-
RevQchgTEn
RevQchgAEn
RevQchgBEn
RevQchgCEn
RevPchgTEn
RevPchgAEn
RevPchgBEn
RevPchgCEn
Reserved.
This bit determines whether to enable the interrupt when the THDUOv bit (b11, SysStatus1) is set.
0: disable (default)
1: enable
This bit determines whether to enable the interrupt when the THDIOv bit (b10, SysStatus1) is set.
0: disable (default)
1: enable
Reserved.
These bits determine whether to enable the corresponding interrupt when any of the direction change bits (b7~b0, SysStatus1) is
set.
0: disable (default)
1: enable
6.2.3 SPECIAL CONFIGURATION REGISTERS
ZXConfig
Zero-Crossing Configuration
Address: 07H
Type: Read/Write
Default Value: 0001H
Bit
Name
15:13
ZX2Src[2:0]
12:10
ZX1Src[2:0]
9:7
ZX0Src[2:0]
Description
These bits select the signal source for the ZX2, ZX1 or ZX0 pins.
Code
011
000
001
010
111
100
101
110
Source
Fixed-0
Ua
Ub
Uc
Fixed-0
Ia
Ib
Ic
6:5
ZX2Con[1:0] These bits configure zero-crossing mode for the ZX2, ZX1 and ZX0 pins.
4:3
ZX1Con[1:0]
2:1
ZX0Con[1:0]
Code
00
01
10
11
Zero-Crossing Configuration
positive zero-crossing
negative zero-crossing
all zero-crossing
no zero-crossing output
This bit determines whether to disable the ZX signals:
0
ZXdis
0: enable
1: disable all the ZX signals to ‘0’ (default).
Register
41
December 9, 2011