ICS952623 Datasheet, PDF (24/27 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
PCI_STOP Asserted
SRC_Stop = Tristate, SRC_Pwrdwn = Tristate
PCI_Stop#
PCI (Free Running)
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1.8mS
Notes:
1. When SRC_Pwrdwn and SRC_Stop are set to tristate, the clock chip will tristate outputs during the assertion of PCI_Stop#
and PWRDWN#.
2. In the case that PCI_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the PCI_Stop# high with the internal rising edges of CPU clock#. This will result in SRC clocks resuming
immediately after the 1.8mS window expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.
0758—02/08/05
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