ICS952623 Datasheet, PDF (17/27 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
CPU_STOP# Functionality
The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.
CPU_STOP# CPU CPU # SRC SRC# 3V66 PCIF/PCI USB/DOT
REF Note
1
Normal Normal Normal Normal 66MHz 33MHz 48MHz 14.318MHz
0
Iref * 6 or Low Normal Normal 66MHz 33MHz 48MHz 14.318MHz
Float
CPU_STOP# - Assertion (transition from '1' to '0')
Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the I2C
CPU_STOP tri-state bit corresponding to the CPU output of interest is programmed to a '0', CPU output will stop CPU_True
= HIGH and CPU_Complement = LOW. When the I2C CPU_Stop tri-state bit corresponding to the CPU output of interest is
programmed to a '1', CPU outputs will be tri-stated.
CPU_STOP#
CPU
CPU#
CPU_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of CPU_Stop# all stopped CPU outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 CPU clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped CPU outputs will be driven High within 10nS of CPU_Stop# de-assertion to
a voltage greater than 200mV.
CPU_Stop#
CPU
CPU#
CPU Internal
Tdrive_CPU_Stop, 10nS >200mV
0758—02/08/05
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