ICS952623 Datasheet, PDF (14/27 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
I²C Table: Overclocking Output Control Register
Byte 9
Pin #
Name
Bit 7
-
Reserved
Bit 6
-
Reserved
Bit 5
-
Reserved
Bit 4
-
Reserved
Bit 3
-
Over Clocking
Bit 2
-
Bit 1
-
Bit 0
-
Over Clocking
Over Clocking
Reserved
Control Function
Reserved
Reserved
Reserved
Reserved
1: over-clk
0: normal mode
Over Clocking
Over Clocking
Reserved
I²C Table: VCO Control Select Bit Control Register
Byte 10
Pin #
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
-
Programming ENABLE ^{Enables prograaming}
bytes 11-14
-
RESERVED
RESERVED
-
RESERVED
RESERVED
-
RESERVED
RESERVED
-
RESERVED
RESERVED
-
RESERVED
RESERVED
-
RESERVED
RESERVED
Bit 0
-
RESERVED
RESERVED
Type
RW
RW
RW
RW
R
R
R
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
-
-
-
-
-
-
-
-
See over clocking per bit 1
and 2
00= +15%, 01 = +20%
10= +5%, 11= +10%
-
-
0
1
DISABLED
-
-
-
-
-
-
-
ENABLED
-
-
-
-
-
-
-
PWD
0
0
0
0
0
0
0
0
PWD
0
0
0
0
0
0
0
0
I²C Table: VCO Frequency Control Register
Byte 11
Pin #
Name
Control Function
Type
0
Bit 7
-
N Div8
N Divider Bit 8
RW
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
M Div6
M Div5
The decimal
RW
-
representation of M
RW
-
M Div4
Div (6:0) is equal to
RW
-
M Div3
reference divider
RW
-
M Div2
value. Default at
RW
-
M Div1
power up = latch-in or
RW
-
Byte 0 Rom table.
M Div0
RW
-
1
PWD
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
0758—02/08/05
14