ICS952623 Datasheet, PDF (11/27 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
I²C Table: Read-Back Register
Byte 0
Bit 7
Bit 6
Pin #
-
-
Bit 5
-
Bit 4
-
Bit 3
-
Name
RESERVED
RESERVED
RESERVED
RESERVED
PCI_STOP#
Bit 2
-
CPU_STOP#
Bit 1
-
FSB
Bit 0
-
FSA
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
PCI STOP# Read
Back
CPU STOP Read
Back
Freq Select 1 Read
Back
Freq Select 0 Read
Back
Type
-
-
-
-
R
R
R
R
0
1
RESERVED
RESERVED
RESERVED
RESERVED
READBACK
READBACK
READBACK of CPU(2:0)
Frequency
PWD
X
X
X
X
X
X
X
X
I²C Table: Spreading and Device Behavior Control Register
Byte 1
Pin #
Name
Control Function
Bit 7
37,38
SRC/SRC#
SRC Free-Running
Control
Bit 6
37,38
SRC
Output Control
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
46,47
43,44
40,41
46,47
43,44
CPUT2/CPUC2
CPUT1/CPUC1
CPUT0/CPUC0
CPUT2/CPUC2
CPUT1/CPUC1
CPU FREE-RUNNING
CONTROL
Output Control
Output Control
Bit 0
40,41
CPUT0/CPUC0
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
FREE-RUN STOPPABLE
Disable
FREE-RUN
FREE-RUN
FREE-RUN
Disable
Disable
Disable
Enable
STOPPABLE
STOPPABLE
STOPPABLE
Enable
Enable
Enable
PWD
0
1
1
1
1
1
1
1
I²C Table: Output Control Register
Byte 2
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
37,38
SRC_PD#
0: Driven in PD#
RW
Driven
Hi-Z
0
Drive Mode
Bit 6
37,38
SRC_Stop#
Drive Mode
0: Driven in
PCI_Stop#
RW
Driven
Hi-Z
0
Bit 5
46,47
CPUT2_PD# Drive
Mode
RW
Driven
Hi-Z
0
Bit 4
43,44
CPUT1_PD# Drive
Mode
0:driven in PD#
1: Tri-stated
RW
Driven
Hi-Z
0
Bit 3
40,41
CPUT0_PD# Drive
Mode
RW
Driven
Hi-Z
0
Bit 2
46,47
CPUT2_Stop Drive
Mode
RW
Driven
Hi-Z
0
Bit 1
43,44
CPUT1_Stop Drive 0:driven when stopped
Mode
1: Tri-stated
RW
Driven
Hi-Z
0
Bit 0
40,41
CPUT0_Stop Drive
Mode
RW
Driven
Hi-Z
0
0758—02/08/05
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