ICS952623 Datasheet, PDF (19/27 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
PD# De-assertion
The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive
mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of
200mV in less than 300µs of PD# deassertion.
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC# 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
Tstable
<1.8mS
Tdrive_PwrDwn#
<300µS, >200mV
3V66_4/VCH Pin Functionality
The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is
3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output
will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising
edge of DOT_48 clock.
3V66
3V66_4/VCH
DOT_48
7.49nS min
0758—02/08/05
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