ICS952623 Datasheet, PDF (22/27 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
CPU_Stop = Driven, CPU_Pwrdwn = Tristate
CPU_Stop#
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
1.8mS
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Pwrdwn is set to tristate and CPU_Stop is set to driven, the clock chip will tristate outputs only during the
assertion of PWRDWN#. Differential clock behavior during the assertion/de-assertion of CPU_Stop# will be unaffected.
2. In the case that CPU_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the CPU_Stop# high with the internal rising edges of clock#. This will result in CPU clocks resuming immediately
after the 1.8mS windows expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.
CPU_Stop = Tristate, CPU_Pwrdwn = Tristate
CPU_Stop#
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
1.8mS
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Stop and CPU_Pwrdwn bits are set to tristate, the clock chip will tristate the outputs during the assertion of
CPU_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.
0758—02/08/05
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