IC-MR Datasheet, PDF (9/44 Pages) IC-Haus GmbH – 13-BIT S&H SIN/COS INTERPOLATOR WITH CONTROLLER INTERFACES

iC-MR 13-BIT S&H SIN/COS
preliminary
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 9/44
ELECTRICAL CHARACTERISTICS
Operating conditions:
VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C, unless otherwise noted.
Item Symbol Parameter
No.
Conditions
Min. Typ.
13-bit Interpolator
C01 tipo
Conversion Time
ACQMODE = 00, see Figure 5
2
C02 AAabs Absolute Conversion Accuracy Vpk() = 250 mV
2
Reset Input / Reset Indication Output NRES
K01 VDDon VDD Turn-on Threshold
increasing voltage at VDD vs. GND
2.6
K02 VDDoff VDD Turn-off Threshold
decreasing voltage at VDD vs. GND
2.3
K03 VDDhys VDD Hysteresis
VDDhys = VDDon - VDDoff
400
K04 Vt()hi
Input Threshold Voltage hi
K05 Vt()lo
Input Threshold Voltage lo
0.8
K06 Vt()hys Input Hysteresis
Vt()hys = Vt()hi - Vt()lo
300 500
K07 Ipu()
Pull-up Current
-750 -300
K08 Vs()lo
Output Saturation Voltage lo
I() = 4 mA
K09 Isc()lo
Output Short-Circuit Current lo V() = 0.4 V...VDD
4
Oscillator
M01 fosc
Internal Oscillator Frequency
15
EEPROM Interface SCL, SDA
N01 Vs()lo
Saturation voltage lo
I() = 4 mA
N02 Isc()
Short-Circuit Current lo
4
N03 Vt()hi
Input Threshold Voltage hi
N04 Vt()lo
Input Threshold Voltage lo
0.8
N05 Vt()hys Input Hysteresis
Vt()hys = Vt()hi - Vt()lo
100 250
N06 Ipu()
Input Pull-up Current
V() = 0 V...VDD - 1 V
-750 -300
N07 Vpu()
Input Pull-up Voltage
Vpu() = VDD - V(), I() = -5 µA
N08 fclk()
Clock Frequency at SCL
100 120
N09 tbusy()cfg Duration of Configuration Phase IBP not adjusted;
read in of EEPROM
5
no EEPROM connected
1
Serial Interface MAI, SLO, SLI
O01 Vt()hi
Threshold Voltage hi at SLI, MAI
O02 Vt()lo
Threshold Voltage lo at SLI, MAI
0.8
O03 Vt()Hys Hysteresis at SLI, MAI
Vt()hys = Vt()hi - Vt()lo
300 500
O04 Ipu()
Pull-up Current at MAI
-150 -60
O05 Ipd()
Pull-down Current at SLI
8
60
O06 fclk()
Permissible Clock Frequency at SSI protocol
MAI
BiSS C protocol
SPI
O07 tp()
Propagation Delay at SLO versus
10
Clock Edge MAI
O08 tbusy() Processing Time
ACQMODE = 00, see Figure 5
t()ipo
O09 t_timeout
Adaptive Timeout
1/fosc
O10 Vs()hi
Saturation Voltage hi at SLO
O11 Vs()lo
Saturation Voltage lo at SLO
O12 Isc()hi
Short-circuit Current hi at SLO
O13 Isc()lo
Short-circuit Current lo at SLO
Parallel Interface D(7...0), NWR, NRD, NL, NCS
P01 Vt()hi
Threshold Voltage hi
P02 Vt()lo
Threshold Voltage lo
P03 Vt()hys Input Hysteresis
P04 Ipu()
Pull-up Current at D(7...0)
Vs()hi = VDD - V(), I() = -4 mA
I() = 4 mA
V() = 0 V...VDD - 0.4 V
V() = 0.4 V...VDD
D(7...0) as input
D(7...0) as input
D(7...0) as input, Vt()hys = Vt()hi - Vt()lo
-80
4
0.8
300 500
-70 -30
Max.
4.3
4.0
2
-60
400
80
400
80
2
-60
0.4
130
2
-8
150
4
10
10
50
1.5*t_MAS
+
3/fosc
400
400
-4
80
2
-5
Unit
µs
LSB
V
V
mV
V
V
mV
µA
mV
mA
MHz
mV
mA
V
V
mV
µA
V
kHz
ms
ms
V
V
mV
µA
µA
MHz
MHz
MHz
ns
mV
mV
mA
mA
V
V
mV
µA