IC-MR Datasheet, PDF (33/44 Pages) IC-Haus GmbH – 13-BIT S&H SIN/COS INTERPOLATOR WITH CONTROLLER INTERFACES

iC-MR 13-BIT S&H SIN/COS
preliminary
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 33/44
registers 0x61 and 0x67 are bypassed; only 24 bits of
singleturn and 16 bits of multiturn data are output.
FULL_CYC
Addr. 0x18; bit 5
R/W
Code
Function
0
24-bit ST / 16-bit MT
1
26-bit ST / 24-bit MT
Table 49: Cyclic telegram length
A CRC is formed across the output data (with the poly-
nomial x ¹⁶ + x ¹⁴ + x ¹¹ + x ¹⁰ + x ⁹ + x ⁷ + x ⁵ + x ³ + x ¹ + 1
(0x14EAB), start value 0xFFFF). The check sum is re-
formed for each cyclic transmission and is only valid
for the duration of this transmission. The follow-
ing sequence applies to the shortened output format
(FULL_CYC = 0):
Data sequence shortened format (FULL_CYC = 0)
Byte No.
Data
Register
1
Status byte
STAT(7:0)
2
Singleturn Lo byte
ST(9:2)
3
Singleturn Mid byte ST(17:10)
4
Singleturn Hi byte
ST(25:18)
5
Multiturn Lo byte
MT(7:0)
6
Multiturn Mid byte
MT(15:8)
7
Life counter
LC(7:0)
8
Error byte
ERR(7:0)
9
Temperature Lo byte TEMP(7:0)
10
Temperature Hi byte TEMP(15:8)
11
CRC Lo byte
CRC(7:0)
12
CRC Hi byte
CRC(15:8)
Address
0x60
0x62
0x63
0x64
0x65
0x66
0x68
0x69
0x6A
0x6B
0x6C
0x6D
Table 50: Data sequence shortened output format
If more bytes are read out in cyclic operation, a zero
is always output. In full output format (FULL_CYC = 1)
the data is output in the following order:
Data sequence complete format (FULL_CYC = 1)
Byte No.
Data
Register
1
Status byte
STAT(7:0)
2
Singleturn Ext byte
ST(1:0)
3
Singleturn Lo byte
ST(9:2)
4
Singleturn Mid byte ST(17:10)
5
Singleturn Hi byte
ST(25:18)
6
Multiturn Lo byte
MT(7:0)
7
Multiturn Mid byte
MT(15:8)
8
Multiturn Hi byte
MT(23:16)
9
Life counter
LC(7:0)
10
Error byte
ERR(7:0)
11
Temperature Lo byte TEMP(7:0)
12
Temperatur Hi byte
TEMP(15:8)
13
CRC Lo byte
CRC(7:0)
14
CRC Hi byte
CRC(15:8)
Address
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
Table 51: Data sequence complete output format