IC-MR Datasheet, PDF (11/44 Pages) IC-Haus GmbH – 13-BIT S&H SIN/COS INTERPOLATOR WITH CONTROLLER INTERFACES

iC-MR 13-BIT S&H SIN/COS
preliminary
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 11/44
OPERATING CONDITIONS: PARALLEL I/O INTERFACE
Operating conditions: VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C
Item Symbol Parameter
No.
Conditions
Min.
I001 tsAW
Setup Time:
50
addresses stable before NWR hi → lo
I002 t_hWA
Hold Time:
50
addresses stable after NWR lo → hi
I003 tsDW
Setup Time:
50
data stable before NWR hi → lo
I004 t_hWD
Hold Time:
50
data stable after NWR lo → hi
I005 tWL
Signal Duration:
80
NWR at low level
I006 tRL
Signal Duration:
80
NRD at low level
I007 tpRD1
Propagation Delay:
CL = 10 pF
50
data stable after NRD hi → lo
I008 tpRD2
Propagation Delay:
80
data bus high ohmic after NRD lo → hi
I009 tWW
Signal Duration:
80
between NWR lo → hi and hi → lo
I010 tWR
Signal Duration:
80
between NWR lo → hi and NRD hi → lo
or NRD lo → hi and NWR hi → lo
I011 tRR
Signal Duration:
80
between NRD lo → hi and hi → lo
I012 tCL
Signal Duration:
80
between NCS hi → lo and NRD hi → lo
or NCS hi → lo und NWR hi → lo
I013 tCH
Signal Duration:
80
between NRD lo → hi and NCS lo → hi
Unit
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NCS
D(7:0)
NWR
NRD
tCL
ADDRESS
tsAW
thAW
DATA_IN
tsDW
thDW
tCH
DATA_OUT
tpRD1
tpRD2
tWL
tWW
tWR
tRL
tRR
Figure 3: Parallel interface timing.