IC-MR Datasheet, PDF (30/44 Pages) IC-Haus GmbH – 13-BIT S&H SIN/COS INTERPOLATOR WITH CONTROLLER INTERFACES

iC-MR 13-BIT S&H SIN/COS
preliminary
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 30/44
Accessing external memory banks
Register banks 2 to 31 store data in an external EEP-
ROM. If an address is accessed which is not physically
present on iC-MR (see Figure 16), communication with
the external EEPROM is initiated. If the parallel inter-
face or serial interface is active in SPI mode, the end
of I²C communication can be recognized by reading
out the status byte (address 0x60, bit 2 BUSY). Only
after this is it possible to again access the internal reg-
isters or external EEPROM registers. When the serial
interface is run in BiSS protocol, iC-MR automatically
requests the processing time necessary for EEPROM
access.
Read and write accesses to data in the external EEP-
ROM may only be made if an EEPROM is connected
up when iC-MR is started. Autoincrement accesses
to external addresses are not possible. Error bit
ERR_KNF is updated following each external access
(e.g. it is set if the storage time on the EEPROM is
undershot, or cancelled if access was successful).
Startup and selection of I/O interface
Register INTCFG defines which I/O interface is used.
Either a parallel or serial interface is available. The se-
rial interface can be run on BiSS, SSI, or SPI protocol.
Only one of the two interfaces may be active. During
the startup phase register INTCFG is set by the con-
nected EEPROM being read out. During operation the
register can be altered, for example to write an EEP-
ROM which iC-MR starts with a different I/O interface.
Figure 17: EEPROM read access
Two read accesses are needed to read out data from
an address on the EEPROM (for the parallel interface
and serial interface in SPI mode only). The first read
access initiates communication with the EEPROM; at
the end of communication the read data is stored in a
temporary register on iC-MR. This temporary register
data is supplied on the next read access to an exter-
nal address. At the same time communication with the
EEPROM is again started on this access. This enables
a large area to be read out quickly, as the next readout
address can already be created to read out the tempo-
rary register.
If an EEPROM data CRC is invalid (after up to 3 read-
out trials) all registers are zeroed and the serial in-
terface is activated with SSI protocol, but pin SLO is
kept permanently high (at VDD). This state is main-
tained until the CRC verification of renewed configu-
ration data was executed successfully (in SSI mode
register write access is permitted).
INTCFG
Code
11
10
01
00
Note
Addr. 0x18; bit 7...6
Function
Parallel interface
Serial interface with SPI protocol
Invalid value
Serial interface with BiSS/SSI protocol*
*) Switching BiSS/SSI with register NESSI
(R/W)
Table 47: Interface selection
Without an EEPROM the pin state of SCL and SDA is
evaluated on startup; INTCFG(1) takes on the value
at pin SCL, with INTCFG(0) assuming the value at pin
SDA.
Figure 18: EEPROM write access
SCL level
1
1
0
0
Startup without EEPROM
SDA level Activated interface
1
Parallel interface
0
Serial interface with SPI protocol
1
Invalid value
0
Serial interface with BiSS/SSI proto-
col
Table 48: Interface selection without EEPROM