IC-MR Datasheet, PDF (2/44 Pages) IC-Haus GmbH – 13-BIT S&H SIN/COS INTERPOLATOR WITH CONTROLLER INTERFACES

iC-MR 13-BIT S&H SIN/COS
preliminary
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 2/44
DESCRIPTION
Device iC-MR is a universal sine-to-digital converter
with signal conditioning and various interfaces for
configuration and data communication. Microcon-
trollers can be connected up through a parallel I/O
interface with an 8-bit bus width (12.5 MHz) or using
a serial I/O interface (4-pin SPI, 20 MHz). The serial
I/O interface can function as a sensor interface either
in BiSS C protocol (up to 10 MHz, bidirectional) or in
SSI protocol (up to 4 MHz).
In the analog signal path iC-MR has precision input
amplifiers with an adjustable gain for differential or
referenced voltage signals of 10 mV peak to 1 V peak
or for current signals of approx. 10 µA to 300 µA (in-
put pins PSI, NSI, PCI, and NCI). A separate mea-
surement input (VREF) enables signals to be refer-
enced to the sensor’s reference voltage.
The downstream signal conditioning unit can com-
pensate for typical sine/cosine sensor signal errors,
such as offset, amplitude, and phase errors. The
conditioned signals are filtered and output through
analog line drivers with an amplitude of typically
250 mV (output pins PSO, NSO, PCO, and NCO). A
differential 1 Vpp signal to 100 Ω is available for line
transmission.
A control signal is gained from the conditioned sig-
nals to stabilize the sine/cosine output signals. This
can adjust the transmitting LED of optical encoder
systems using the integrated 50 mA driver stage (out-
put ACO). With magnetic sensors this driver output
supplies the MR measuring bridges or can be used
to feedback the bridge supply voltage. By tracking
the sensor supply, sensor temperature and ageing ef-
fects are compensated for, the input signals are sta-
bilized, and precise calibration of the input signals is
maintained. This makes a constant interpolation ac-
curacy possible across the entire operating tempera-
ture range.
At the same time the sensor is monitored for proper
functioning. The amplitude and offset of the input sig-
nals at pins PSI, NSI, PCI, and NCI are checked, en-
abling wire-breakage or short circuits to be detected.
The control unit operating limits are also monitored
so that an alarm can be signaled through the I/O in-
terface and/or at error output NERR, depending on
the configuration, with dirt or ageing of optical sys-
tems.
Sine-to-digital conversion is performed by a fast inter-
polator with a sample-&-hold circuit which resolves a
sine period with 13 bits either continuously or on re-
quest. In parallel and independent of the interpola-
tor a configurable 37-bit period counter logs the sine
and cosine zero crossings. This period counter is
programmable and can take its start value from the
serial absolute data interface (ADI); the correspond-
ing interface master operates either in BiSS C or SSI
protocol.
For position measurement applications iC-MR differ-
entiates between multiturn and singleturn data using
a selectable intersection on the period counter. The
position can be corrected accordingly using the mul-
titurn and singleturn offset values.
An integrated 12-bit A/D converter digitizes linear
measurement voltages at pin ADC for the evaluation
of KTY temperature sensors, for example. Measure-
ment of the calibratable converter is observed by set-
table threshold values so that a permissible operating
temperature range with a lower and upper tempera-
ture threshold can be monitored.
After power-on iC-MR collects its CRC protected
configuration data from an external I²C-EEPROM or
waits for the configuration from one of the I/O inter-
faces. An undervoltage reset zeroes internal reg-
isters and is shown as a reset pulse at pin NRES,
which also serves as a reset input (low active).
Errors can always be masked and allocated to an
error byte (and displayed at error message output
NERR) or a warning byte. The internal status reg-
isters are available to the I/O interfaces which have a
number of different commands (software reset, mem-
ory verification, and error simulation).