IC-MU150 Datasheet, PDF (62/64 Pages) IC-Haus GmbH – MAGNETIC OFF-AXIS POSITION ENCODER - POLE WIDTH 1.50MM

iC-MU150 MAGNETIC OFF-AXIS
POSITION ENCODER - POLE WIDTH 1.50MM
DESIGN REVIEW: Notes On Chip Functions
Rev B1, Page 62/64
iC-MU150 0
No.
Function, Parameter/Code
1
3-track Nonius systems with two iC-MU
MPC ≥ 0x7
2
SPI interface (MODEA = 0x0, 0x1),
Read/Write REGISTER(single) with
access to EEPROM
3
SSI interface Gray coded
MODEA = 0x4;
GSSI = 0x1;
OUT_ZERO = 0x0
4
SSI interface Gray coded with error bit
MODEA = 0x5 or 0x6;
GSSI = 0x1;
OUT_ZERO = 0x0
Description and Application Notes
The period counter consistency error verification NON_CTR of the multiturn iC-MU
(see Figure 42, iC-MU(2)) must be switched off → NCHK_NON = 0x1.
SPI command sequence as in Figure 31. The end of a Read/Write
REGISTER(single) command to an EEPROM address can be detected by
checking the status bit BUSY. Register Status/Data and SPI-STATUS change
from 0x02 (Busy) to 0x00. The status bits VALID/FAIL are without functionality. A
successful I²C communication between iC-MU and the EEPROM can be checked
via STATUS1 flag EPR_ERR = 0.
The level of the SSI output pin (signal SLO) can be "1" or "0" during timeout t_tout
(see Figure 5). Therefore, a SSI timeout may not be detected by a SSI master in
any case.
To obtain a reliable SSI timeout set parameter OUT_ZERO = 0x1 (includes a zero
bit after position data) and send an additional clock pulse.
The SSI position data is not converted correctly into Gray code.
By setting parameter OUT_ZERO = 0x1 (includes a zero bit after position data)
and sending an additional clock pulse and subsequently ignoring the additional
ZERO bit, the singleturn data is converted correctly into Gray code.
Table 119: Notes on chip functions regarding iC-MU150 chip release 0
iC-MU150 1
No.
Function, Parameter/Code
1
SPI interface (MODEA = 0x0, 0x1),
Read/Write REGISTER(single) with
access to EEPROM
2
SSI interface Gray coded
MODEA = 0x4;
GSSI = 0x1;
OUT_ZERO = 0x0
3
SSI interface Gray coded with error bit
MODEA = 0x5 or 0x6;
GSSI = 0x1;
OUT_ZERO = 0x0
Description and Application Notes
SPI command sequence as in Figure 31. The end of a Read/Write
REGISTER(single) command to an EEPROM address can be detected by
checking the status bit BUSY. Register Status/Data and SPI-STATUS change
from 0x02 (Busy) to 0x00. The status bits VALID/FAIL are without functionality. A
successful I²C communication between iC-MU and the EEPROM can be checked
via STATUS1 flag EPR_ERR = 0.
The level of the SSI output pin (signal SLO) can be "1" or "0" during timeout t_tout
(see Figure 5). Therefore, a SSI timeout may not be detected by a SSI master in
any case.
To obtain a reliable SSI timeout set parameter OUT_ZERO = 0x1 (includes a zero
bit after position data) and send an additional clock pulse.
The SSI position data is not converted correctly into Gray code.
By setting parameter OUT_ZERO = 0x1 (includes a zero bit after position data)
and sending an additional clock pulse and subsequently ignoring the additional
ZERO bit, the singleturn data is converted correctly into Gray code.
Table 120: Notes on chip functions regarding iC-MU150 chip release 1