IC-MU150 Datasheet, PDF (14/64 Pages) IC-Haus GmbH – MAGNETIC OFF-AXIS POSITION ENCODER - POLE WIDTH 1.50MM

iC-MU150 MAGNETIC OFF-AXIS
POSITION ENCODER - POLE WIDTH 1.50MM
CONFIGURATION PARAMETERS
Rev B1, Page 14/64
Analog parameters (valid for all channels)
CIBM:
Bias current settings (p. 19)
ENAC:
Amplitude control unit activation (p. 20)
Signal conditioning
GC_M:
Master gain range selection (p. 19)
GF_M:
Master gain (p. 19)
GX_M:
Master cosine signal gain adjustment
(p. 19)
VOSS_M: Master sine offset adjustment (p. 20)
VOSC_M: Master cosine offset adjustment (p. 20)
PH_M:
Master phase adjustment (p. 20)
PHR_M: Master phase adjustment range (p. 20)
GC_N:
Nonius gain range selection (p. 19)
GF_N:
Nonius gain (p. 19)
GX_N:
Nonius cosine signal gain adjustment
(p. 19)
VOSS_N: Nonius sine offset adjustment (p. 20)
VOSC_N: Nonius cosine offset adjustment (p. 20)
PH_N:
Nonius phase adjustment (p. 20)
PHR_N: Nonius phase adjustment range (p. 20)
Digital parameters
TEST:
Adjustment modes/iC-Haus test modes
(p. 21)
CRC16:
EEPROM configuration data checksum
(p. 23)
CRC8:
EEPROM offset and preset data
checksum (p. 23)
NCHK_CRC: Cyclic check of CRC16 and CRC8
(p. 23)
BANKSEL: Serial Access: Bank register (p. 48)
RPL:
Register Access Control (p. 52)
RPL_RESET: Serial Access: Register for reset register
access restriction (p. 52)
EVENT_COUNT: Serial Access: Event counter (p. 57)
HARD_REV: serial address: revision code (p. 51)
Configurable I/O interface
MODEA: I/O port A configuration (p. 26)
MODEB: I/O port B configuration (p. 26)
NTOA:
Adaptive Timeout (p.29)
PA0_CONF: Configurable commands to pin PA0 A
(p. 59)
ROT_ALL: Code direction (p. 28)
OUT_MSB: Output shift register configuration: MSB
used bits (p. 28)
OUT_LSB: Output shift register configuration: LSB
used bits (p. 28)
OUT_ZERO:
Output shift register configuration:
number of zeros inserted after the used
bits and before an error/warning (p. 28)
MODE_ST: Data output (p. 27)
GSSI:
Gray/binary data format (p. 31)
RSSI:
Ring operation (p. 31)
Multiturn interface
MODE_MT: Multiturn mode (p. 40)
SBL_MT: Multiturn synchronization bit length
(p. 40)
CHK_MT: Cyclic check of the multiturn value
(p. 41)
GET_MT: MT interface daisy chain (S. 43)
ROT_MT: Code direction external multiturn (p. 41)
ESSI_MT: Error Bit external multiturn (p. 41)
SPO_MT: Offset external multiturn (p. 41)
Converter and nonius calculation
FILT:
Digital filter settings (p. 37)
MPC:
Master period count (p. 37)
LIN:
Linear scanning (p. 38)
SPO_x:
Offset of nonius to master
(x=BASE,0-14) (p. 38)
NCHK_NON: Cyclic check of the nonius value (low
active) (p. 39)
Incremental output ABZ, STEP/DIR and CW/CCW
RESABZ: Incremental interface resolution
ABZ,STEP-DIR,CW/CCW (p. 44)
LENZ:
Index pulse length (p. 45)
INV_A:
A/STEP/CW signal inversion (p. 44)
INV_B:
B/DIR/CCW signal inversion (p. 44)
INV_Z:
Z/NCLR signal inversion (p. 44)
SS_AB:
System AB step size (p. 45)
FRQAB: AB output frequency (p. 46)
CHYS_AB: Converter hysteresis (p. 46)
ENIF_AUTO: Incremental interface enable (p. 46)
UVW commutation signals
PPUVW: Number of commutation signal pole
pairs (p. 47)
PP60UVW: Commutation signal phase position
(p. 47)
OFF_UVW: Commutation signal start angle (p. 47)
OFF_COM: serial address: absolute position offset
for UVW calculation engine changed by
nonius (S. 47)
Status/command registers and error monitoring
CMD_MU: serial address: command register (p. 56)
STATUS0: serial address: status register 0 (p. 54)
STATUS1: serial address: status register 1 (p. 54)
CFGEW: Error and warning bit configuration
(p. 54)
EMTD:
Minimum error message duration (p. 55)
ACC_STAT: Output configuration status register
(S. 54)
ACRM_RES: Automatic reset with master track
amplitude errors (p. 39)