IC-MU150 Datasheet, PDF (3/64 Pages) IC-Haus GmbH – MAGNETIC OFF-AXIS POSITION ENCODER - POLE WIDTH 1.50MM

iC-MU150 MAGNETIC OFF-AXIS
POSITION ENCODER - POLE WIDTH 1.50MM
CONTENTS
Rev B1, Page 3/64
PACKAGING INFORMATION
5
PIN CONFIGURATION DFN16-5x5
(topview) . . . . . . . . . . . . . . . . . 5
PACKAGE DIMENSIONS . . . . . . . . . . . 6
Serial interface:
Configuring the data format and data
length . . . . . . . . . . . . . . . . . . . 27
BiSS C interface . . . . . . . . . . . . . . . . 29
SSI interface . . . . . . . . . . . . . . . . . . 30
ABSOLUTE MAXIMUM RATINGS
7
SPI interface: general description . . . . . . . 32
THERMAL DATA
SPI interface: Command ACTIVATE . . . . . 32
7
SPI interface: Command SDAD transmission 33
ELECTRICAL CHARACTERISTICS
8
OPERATING REQUIREMENTS
10
Multiturn Interface . . . . . . . . . . . . . . . 10
I/O Interface . . . . . . . . . . . . . . . . . . 11
PRINCIPLE OF MEASUREMENT
13
SPI interface: Command SDAD status . . . . 34
SPI interface: Command Read REGISTER
(single) . . . . . . . . . . . . . . . . . . 34
SPI interface: Command Write REGISTER
(single) . . . . . . . . . . . . . . . . . . 35
SPI interface: Command REGISTER
status/data . . . . . . . . . . . . . . . . 35
Rotative measuring system . . . . . . . . . . 13 _{CONVERTER AND NONIUS CALCULATION}
37
Linear measuring system . . . . . . . . . . . 13
Converter principle . . . . . . . . . . . . . . . 37
CONFIGURATION PARAMETERS
Synchronization mode . . . . . . . . . . . . . 37
14
MT INTERFACE
40
REGISTER ASSIGNMENTS (EEPROM)
16
Configuration of the Multiturn interface . . . . 40
Register assignment (EEPROM) . . . . . . . 16
Construction of a Multiturn system with two
Special BiSS registers . . . . . . . . . . . . . 18
iC-MU150 . . . . . . . . . . . . . . . . . 41
MT Interface Daisy Chain . . . . . . . . . . . 43
SIGNAL CONDITIONING FOR MASTER AND
NONIUS CHANNELS: x = M,N
19 _{INCREMENTAL OUTPUT ABZ,}
Bias current source . . . . . . . . . . . . . . 19
STEP/DIRECTION AND CW/CCW
44
Gain settings . . . . . . . . . . . . . . . . . . 19
Offset compensation . . . . . . . . . . . . . . 20 ^{UVW COMMUTATION SIGNALS}
47
Phase adjustment . . . . . . . . . . . . . . . 20 _{REGISTER ACCESS THROUGH SERIAL}
ANALOG SIGNAL CONDITIONING FLOW: x =
M,N
21
1. Conditioning the BIAS current . . . . . . . 21
2. Positioning of the sensor . . . . . . . . . . 21
INTERFACE (SPI AND BISS)
48
Register mapping Configuration, Bank 0:
Addresses 0x00-0x3F . . . . . . . . . . 48
Register mapping static part: Addresses
0x40-0xBF . . . . . . . . . . . . . . . . 50
3.a Test modes analog master and analog
nonius . . . . . . . . . . . . . . . . . . . 21
3.b Test mode CNV_x . . . . . . . . . . . . . 21
Address sections/Register protection level . . 52
Overview Register access: memory mapping,
Register protection levels . . . . . . . . 53
4. Track offset SPON . . . . . . . . . . . . . 22
STATUS REGISTER AND ERROR MONITORING 54
I2C INTERFACE AND STARTUP BEHAVIOR 23
Status register . . . . . . . . . . . . . . . . . 54
I2C interface / CRC . . . . . . . . . . . . . . 23
Error and warning bit configuration . . . . . . 54
Startup behavior . . . . . . . . . . . . . . . . 24
COMMAND REGISTER
56
CONFIGURABLE I/O INTERFACE
26
Description of implemented commands . . . 56
Setting the interfaces . . . . . . . . . . . . . 26
Configurable NPRES Pin . . . . . . . . . . . 58