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IC-MN Datasheet, PDF (53/59 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION | |||
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iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
iC-MN internal
linear address-
space divided into n
banks of size 64
byte
ADR
0x00
address-space visible via BiSS
(CFG_E2P > 000)
bank n-1
(e.g. CFG_E2P > 101; n=32)
bank 3
...
bank 2
ADR
0x00
bank 1
bank 0
0x3F
0x40
Rev D1, Page 53/59
0x7F
0x80
0xBF
0xC0
0xFF
0x3F
0x40
0x7F
BANKSEL
EDSBANK
profile ID
serial number
SLAVE-registers
STATUS
BiSS-ID
selects
Figure 29: Principle of bank-wise memory addressing
Register access can be restricted via PROT_E2P (see
Table 100). PROT_E2P = 10 selects safety level 2, a
shipping mode with limited access. Shipping 2 can be
set back to level 1 (shipping 1), for which purpose the
content of address 0x43 must be written anew.
PROT_E2P(1:0) Addr. 0x43; bit 1:0
Code
Mode
Access Limitation
(see Figure 30 and 31)
00
Conï¬guration Mode,
RP0
free access
01
Conï¬guration Mode,
RP1
limited access
10
Shipping Mode 1,
RP2
reset to RP1 is possible
11
Shipping Mode 2,
RP2
reset is not possible
Table 100: Register Access Control
Sections CONF, EDS and USER are protected at dif-
ferent levels in shipping mode for read and write ac-
cess.
PROT_E2P(1:0) Addr. 0x43; bit 1:0
Range
RPL*
CONF
EDS
RP0
r/w
r/w
RP1
STATUS n/a r/w
r/w for others
RP2
n/a
r only
Note
* Register Protection Level
USER
r/w
r/w
r/w
Table 101: Register Read/Write Protection Levels
(n/a: iC-MN refuses access to those regis-
ter addresses.)
Figure 30 shows the static memory area and Figure 31
the area which can be altered by BANKSEL. The BiSS
register access limitations which are generated by pa-
rameter PROT_E2P are marked âR/Wâ for read/write
access and âRâ for read only. The original site of data
returned by access to the BiSS register is designated
by âRAMâ for iC-MNâs internal RAM, by âE2Pâ for the
EEPROM and by âINTâ for those of iC-MNâs internal
registers which cannot be preloaded on startup.
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