IC-MN Datasheet, PDF (43/59 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
Rev D1, Page 43/59
Status Register
The status register is reached by a read access to ad-
dresses 0x75 to 0x77. In the event of an error the
relevant bit is set and maintained until the status reg-
ister is read out or the command SOFT_RES is per-
formed (with the exception of status bits EPR_ERR
and CMD_EXE). The status register can be accessed
independent of the internal state of operation.
STATUS
Bit Name
7 TH_WRN
6 EPR_ERR
5 FQ_WDR
4 FQ_STUP
3 NON_CTR
2 MT_CTR
1 MT_ERR
0 MT_WRN
Notes
Addr. 0x75; bit 7:0
R
Description of status message
Excessive temperature warning
Configuration error on startup:
- No EEPROM (flag EPR_NO set)
- Invalid check sum (flag EPR_NV set)
Excessive signal frequency on master track*:
on current readout request
Excessive signal frequency on master track*:
during startup
Period counter consistency error:
counted period ↔ calculated Nonius position
Multiturn data consistency error:
counted multiturn ↔ external MT data
Multiturn communication error:
- Error bit set
- CRC error
- No start bit
- General communication error
Multiturn data indicates warning message
(BiSS warning bit set)
*) Relevant for nonius synchronization
modes (MODE_ST = 0x00 to 0x0B); the
warning threshold can be set using
parameter FRQ_TH;
Error indication logic: 1 = true, 0 = false
Table 73: Status register 0x75
STATUS
Bit Name
7 ACS_Max
6 AM_Min
5 AM_Max
4 ACM_Min
3 ACM_Max
2 CT_ERR
1 RF_ERR
0 TH_ERR
Notes
Addr. 0x76; bit 7:0
R
Description of status message
Control error: range at max. limit
Signal error: poor level (master track)
Signal error: clipping (master track)
Control error: range at min. limit
Control error: range at max. limit
Readout cycle repetition to short*
Excessive SSI clock frequency: conversion
data not valid when latching data for output.
Excessive temperature error
*) Relevant for nonius synchronization
modes MODE_ST = 0x00 to 0x07
(calculation routines must end before a new
request is received)
Error indication logic: 1 = true, 0 = false
Table 74: Status register 0x76
EPR_ERR indicates that no EEPROM was found on
system startup (EPR_NO) or that a CRC error was rec-
ognized for the internal setup (EPR_NV). If no EEP-
ROM has been recognized, EPR_ERR remains set
even after SOFT_RES.
CMD_CNV and CMD_EXE are signaled on the same
status bit and not stored, as opposed to the other
status bits. CMD_CNV is set on the initialization
of a command which requires the internal converter.
CMD_EXE is set on commands which employ the in-
ternal data bus.
STATUS
Addr. 0x77; bit 7:0
R
Bit Name
Description of status message
7 CMD_EXE Command execution in progress, or
CMD_CNV iC-MN in startup phase
6 AN_Min Signal error: poor level (nonius track)
5 AN_Max Signal error: clipping (nonius track)
4 ACN_Min Control error: range at min. limit
3 ACN_Max Control error: range at max. limit
2 AS_Min Signal error: poor level (segment track)
1 AS_Max Signal error: clipping (segment track)
0 ACS_Min Control error: range at min. limit
Notes
Error indication logic: 1 = true, 0 = false
Table 75: Status register 0x77
Non-Volatile Diagnosis Memory
By enabling E2EPR all status messages can be stored
to the external EEPROM the first time they occur
(physical EEPROM addresses 0x75 to 0x77).
On a system startup iC-MN reads in the status mes-
sages already stored in the EEPROM. As soon as an
error message occurs which has not been noted in the
external memory the corresponding status register bit
is transfered to the EEPROM. This way a "cumulative"
error register is compiled in which all messages are
stored which occur during operation. Only the current
errors can be read out via the status register (BiSS ad-
dresses 0x75 to 0x77).
The cumulative errors which are stored at EEPROM
addresses 0x75 to 0x77 can only be read out via BiSS
with CFG_E2P > 000 and PROT_E2P = 00 to bank 1,
address 0x35-0x37 (see page 52 ff. for memory map).
Note: Once configuration has been completed and be-
fore the system is delivered the data at the EEPROM
addresses 0x75 to 0x77 should be initialized with ze-
roes.
E2EPR
Code
0
1
Addr. 0x41; bit 7
Description
Disabled
EEPROM savings of cumulative status messages
enabled
Table 76: Diagnosis memory enable