IC-MN Datasheet, PDF (44/59 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
ERROR AND WARNING BIT
Rev D1, Page 44/59
For the error and warning bit output the logic is always
low active; a logic zero displays an active error or warn-
ing message. With the exception of an external system
error message (read in via I/O pin NERR and assigned
to EXT_ERR) all error codes mentioned in the follow-
ing are stored in the status register should the corre-
sponding error event occur.
featuring open-drain alarm outputs a wired-or bus logic
can be installed.
EXT_ERR
Code
0
1
Description
No external error
External component indicating an error to pin
NERR
The allocation of error messages to the error and warn-
ing bit is either fixed or can be varied with the CFGEW
parameter. The following tables explain the fixed and
optional visibility.
Table 79: External error message
Fixed Allocation Of Error Messages
Message
Visibility via error bit Conditions
EPR_NV*
EPR_NO
CMD_CNV**
CT_ERR
•
None
RF_ERR
•
Visible when
NBISS = 1
MT_ERR
MT_CTR
•
Visible when
MODE_MT = 01, 10
NON_CTR
FQ_STUP
•
Visible when
MODE_ST set for
nonius synch.
Notes
*) Reset by command SOFT_RES
**) CMD_CNV is also visible for warning bit.
Table 77: Fixed allocation of messages for error bit in-
dication
CFGEW
Bit
7
6
5
Bit
4
3
2
1
0
Notes
Adr 0x42, bit(7:0)
Visibility for error bit
Ax_MAX, Ax_MIN
EXT_ERR
TH_ERR
Enables additional functions, please refer to the
description given below.
Visibility for warning bit
FQ_WDR
Ax_MAX and Ax_MIN
ACx_MAX and ACx_MIN
TH_WRN
MT_WRN
x = M, S, N
Encoding of bit 7...0:
0 = message enabled, 1 = message disabled
Table 80: Error and warning bit configuration
Message
MT_WRN
TH_WRN
FQ_WDR
ACx_MAX
ACx_MIN
Ax_MAX
Ax_MIN
TH_ERR
EXT_ERR
Notes
Variable Allocation Of Error Messages
Visibility via error bit Visibility via warning
bit
n/a
◦
n/a
◦
n/a
◦
n/a
◦
n/a
◦
◦
◦
◦
◦
◦
n/a
◦
n/a
◦ = configurable via CFGEW
x = M, S, N
Table 78: Variable allocation of error messages for er-
ror/warning bit indication
EXT_ERR can only be configured to the error bit and
is not latched by the status register. It permits iC-MN to
signal an error state of further ICs to the PLC, when the
messaging IC pulls down the NERR pin. With devices
The visibility of the temperature error can be config-
ured on the error bit by CFGEW(5) = 0. The occurrence
of a temperature error then causes:
1. The setpoint of the signal level controller to be
reduced to the lowest setting
2. The analog output voltages to switch to VDD/2 at
outputs PSOUT, NSOUT, PCOUT and NCOUT
3. The RS422 output driving capability to be limited
to 20 mA.
The following must also be taken into account:
• Error messages which are signaled via the error
bit of the serial I/O interface are also indicated by
a low signal at the NERR pin
• Nonius synchronization errors (NON_CTR) are
indicated directly at the NERR pin